Timed mock (90 minutes)

Staff-level: multi-agent, coverage, closure talk.

Timer breakdown

1. 0–15 min: Requirements clarifying — 2 agents + reg + IRQ

2. 15–40 min: Full env diagram + connect_phase narration

3. 40–55 min: Virtual sequence layering

4. 55–70 min: Scoreboard + coverage placement

5. 70–85 min: Debug hooks + regression strategy

6. 85–90 min: Closure/signoff talking points

RUBRIC (score 1–5 each)

  Mechanism accuracy — correct UVM pattern, no magic
  Communication — narrates while sketching
  Pitfalls — cites unprompted
  Test mindset — smoke test + regression hook

STRONG HIRE: mechanism + pitfall + test without prompting
NO HIRE: silent coding, wrong TLM direction, no test plan

Interviewer follow-up traps (sample 10)

• Why virtual sequencer here?

• Passive vs active split?

• Coverage closure metric?

• Waivers process?

• Block vs chip reuse?

• Phase domains?

• Who owns cfg object?

• VIP integration boundary?

• Nightly vs smoke?

• What would you do first week on job?

Strong hire signals

• Narrates DECLARE→TEST without prompting

• Names pitfall unprompted

• Smoke test and regression hook stated

• Asks clarifying protocol questions early

No hire signals

• Silent coding

• Wrong TLM direction on diagram

• No test plan after sketch

• Cannot recover when stuck

CODE LAB FOLLOW-UP: uvm-l10-mock-full-env

Key takeaways

• Complete mock in 90 min wall clock.

• Self-score rubric honestly.