UVM Phases & Simulation Lifecycle

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Part 2 of 15Phases & LifecycleIntermediate

4topics
26lessons

Phases are the contract that lets components written by different teams share one timeline: everything is built before anything is wired, everything is wired before time moves, and the run ends when the components that are busy say they are done. Most end-of-test bugs, from the test that passes at time 0 to the one that hangs for hours, are a broken clause of that contract. This part teaches the contract on the course's DMA bench, then the tools for when it breaks.

What you will be able to do

Draw the full phase schedule, including run_phase running beside the twelve runtime phases, and say what belongs in each phase.
Explain what the phaser does with your code: walk directions, forked threads, phase nodes and states.
Place overrides, configuration and connections in the right phase, and know what the library's base phase methods do for you.
Own the end of a test: objections, drain time, phase_ready_to_end, timeouts, and how a simulation finally stops.
Debug a hang, an early end or a silent pass from the logs, with a repeatable method.

Learning map: the phase system, then build connect and run, then objections, then phase debugging.

The four topics in reading order. The first two explain the schedule and apply it; the last two are about ending the run phase correctly and finding out why it did not.

The four topics

Topic	What it covers
The Phase System	Why phases exist, the full schedule with its common and uvm domains, top-down and bottom-up walks, function versus task phases, exact signatures, and the phaser's nodes, imps and states.
Build, Connect and Run	The DMA bench phase by phase: factory overrides and top-down build, config_db gets, TLM wiring, the time-0 audit, the run window, runtime phases, what super.build_phase() does, and how run_test and timeouts end a simulation.
Objections Deep Dive	How objections propagate and count, drain time, phase_ready_to_end, choosing an end-of-test mechanism, and objections in large benches.
Phase Debugging and End-of-Test Signoff	The extract-check-report chain, phase domains and sync, reset and jump, ordering bugs, custom phases, and a triage playbook for hangs and early ends.

Related topics

Up nextThe Phase System

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What you will be able to do

Draw the full phase schedule, including run_phase running beside the twelve runtime phases, and say what belongs in each phase.

Explain what the phaser does with your code: walk directions, forked threads, phase nodes and states.

Place overrides, configuration and connections in the right phase, and know what the library's base phase methods do for you.

Own the end of a test: objections, drain time, phase_ready_to_end, timeouts, and how a simulation finally stops.

Debug a hang, an early end or a silent pass from the logs, with a repeatable method.

Learning map: the phase system, then build connect and run, then objections, then phase debugging.

The four topics in reading order. The first two explain the schedule and apply it; the last two are about ending the run phase correctly and finding out why it did not.

The four topics

Topic	What it covers
The Phase System	Why phases exist, the full schedule with its common and uvm domains, top-down and bottom-up walks, function versus task phases, exact signatures, and the phaser's nodes, imps and states.
Build, Connect and Run	The DMA bench phase by phase: factory overrides and top-down build, config_db gets, TLM wiring, the time-0 audit, the run window, runtime phases, what super.build_phase() does, and how run_test and timeouts end a simulation.
Objections Deep Dive	How objections propagate and count, drain time, phase_ready_to_end, choosing an end-of-test mechanism, and objections in large benches.
Phase Debugging and End-of-Test Signoff	The extract-check-report chain, phase domains and sync, reset and jump, ordering bugs, custom phases, and a triage playbook for hangs and early ends.