Phase Debugging Hub: Ordering Bugs & Objection Leaks

Overview

Most UVM debug sessions are phase problems in disguise: simulation hangs from objection leaks, instant pass from missing raises, null handles from build order bugs, and silent override failures from wrong method signatures. This hub gives a systematic playbook — tools first, symptom→cause→fix tables, and real case studies.

Sub-lessons in this topic

1. phase-trace-tools — +UVM_PHASE_TRACE, topology print, objection dump.

2. ordering-bug-patterns — build/connect/run ordering failures.

3. objection-leak-triage — raise/drop imbalance diagnosis.

4. phase-mismatch-symptoms — wrong signature, missing super, override gaps.

5. debug-checklist-playbook — step-by-step triage for any phase hang.

6. phase-debug-case-studies — three worked examples with fixes.

Debug toolkit map

[PHASE][UVM] debug toolkit

+uvm_set_action=*_*,UVM_PHASE_,UVM_LOG  (implicit in PHASE_TRACE)
+UVM_PHASE_TRACE          every phase entry/exit
+UVM_OBJECTION_TRACE      every raise/drop + count
+UVM_VERBOSITY=UVM_HIGH   context around traces

in-code:
  uvm_top.print_topology()       (end_of_elaboration)
  phase.phase_done.convert2string()  (objection dump)

simv +UVM_PHASE_TRACE +UVM_OBJECTION_TRACE +UVM_VERBOSITY=UVM_MEDIUM

Key takeaways

• Most phase bugs: missing super, wrong signature, null connect, objection leak.

• +UVM_PHASE_TRACE and +UVM_OBJECTION_TRACE turn guesswork into evidence.

• Use print_topology before run_phase to catch build/connect gaps.

• Guard against silent false pass with check_phase zero-transaction assert.

Common pitfalls

• Adding #delays to fix ordering instead of correcting phase placement.

• Debugging hangs with waveforms before reading objection trace.

• One-character signature typo causing silent override failure.

Triage priority

When a test misbehaves, run through this priority before touching RTL or waveforms:

1. Phase trace — did expected phases run in expected order?

2. Objection trace — is count zero when sim should end? Non-zero when it should run?

3. Topology — did build/connect create the expected component tree?

4. Signatures — do all phase overrides match uvm_component base exactly?

[PHASE][UVM] evidence before speculation

no evidence → no fix
phase trace + objection trace → 80% of hangs diagnosed