Elaboration & Start Hub: Pre-Time-Zero Validation

Overview

After connect_phase, the testbench is fully built and wired — but simulation time has not advanced . Two function phases occupy this gap: end_of_elaboration (bottom-up validation) and start_of_simulation (top-down banners and last-chance setup).

These phases are often thin, but they are the last safe moment to audit structure before run_phase consumes time.

Sub-lessons in this topic

1. end-of-elaboration-checks - structural validation and topology audit.

2. start-of-simulation-setup - banners, config dump, watchdog arming.

3. structural-sanity - invariant assertions before time 0.

4. banner-diagnostics - self-documenting logs for regression triage.

5. pre-time-zero-contract - what is legal before run_phase.

6. elaboration-debug - triage for elaboration and start failures.

[PHASE][UVM] pre-run phase pair

  connect_phase complete
       │
       ▼
  end_of_elaboration_phase  (bottom-up)
       │  print_topology, structural asserts
       ▼
  start_of_simulation_phase (top-down)
       │  banners, cfg dump, arm watchdogs
       ▼
  run_phase begins (time may advance)

function void end_of_elaboration_phase(uvm_phase phase);
  super.end_of_elaboration_phase(phase);
  uvm_top.print_topology();
endfunction

function void start_of_simulation_phase(uvm_phase phase);
  super.start_of_simulation_phase(phase);
  `uvm_info("BANNER", $sformatf("test=%s seed=%0d",
    get_type_name(), cfg.seed), UVM_LOW)
endfunction

Key takeaways

• end_of_elaboration = validate structure; start_of_simulation = document intent.

• Both are zero-time function phases — no waiting, no pin activity.

• print_topology here saves hours of blind run_phase debug.

Common pitfalls

• Skipping topology print and debugging missing components in run_phase.

• Driving reset or waiting for clocks in start_of_simulation.

• Treating these phases as optional — they are the elaboration audit gate.

Pre-time-zero contract summary

Use this quick reference when reviewing components for phase discipline at the build/connect/elaboration boundary.

Phase pair rules

[PHASE][UVM] elaboration/start rules

ALLOWED:
  super calls for both phases
  print_topology / print_config
  structural assert (counts, null checks on members)
  banner and metadata logging
  arming static watchdogs (no time consumption)

FORBIDDEN:
  #delay, wait(), @(event)
  sequence.start()
  driving DUT pins
  creating new uvm_components

• end_of_elaboration runs bottom-up — children validate before parents.

• start_of_simulation runs top-down — test banner before children.

• Move any time-consuming activity to run_phase.

[PHASE] elaboration → run handoff

elaboration/start deliver:
  - audited topology (logged)
  - documented cfg (logged)
  - structural invariants checked

run_phase expects:
  - frozen structure
  - known cfg snapshot in log
  - no surprise missing components

Common pitfalls

• Re-reading config_db for first-time mandatory setup here — too late.

• Creating components to 'fix' connect misses — wrong phase.

• Heavy computation in start_of_simulation slowing every test.