Part 2 · Phases & Lifecycle · Intermediate
Phase Overview Hub: Scheduler Traversal & the Common List
Hub — uvm_phase scheduler overview, the nine common phases, top-down vs bottom-up rules, full timeline map, scheduler vs user code boundaries, and phase-overview debug.
Overview
The UVM phase scheduler walks the component tree and invokes the same named callback on every component for each phase. The order of phases is fixed; the traversal direction changes per phase.
Only run_phase (and the 12 runtime sub-phases) consume simulation time. All other common phases are zero-time function phases.
Sub-lessons in this topic
phase-scheduler-overview — how uvm_phase and the scheduler cooperate.
common-phase-list — the nine common phases and what each does.
traversal-order-rules — top-down vs bottom-up and why.
phase-timeline-map — build, run, cleanup on one axis.
scheduler-vs-user-code — what the library owns vs what you implement.
phase-overview-debug — trace switches and traversal verification.
[UVM][PHASE] scheduler at a glance
for each phase in fixed order:
scheduler selects traversal direction (TD or BU)
visits every uvm_component in tree
calls <phase>_phase(phase) on each node
waits for task phases / sub-phases to complete
advances to next phase
user code:
implement callbacks
never call phase methods on neighbors directly// The scheduler calls YOU — not the other way around
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
// wiring only — scheduler already ran all build_phase callbacks
endtaskKey takeaways
Nine common phases run in a fixed global order for the entire testbench.
Traversal direction alternates to satisfy structural dependencies.
run_phase is the only common phase that advances simulation time.
Common pitfalls
Manually calling a neighbor's phase method — breaks scheduler contract.
Assuming connect_phase is top-down — it is bottom-up.
Expecting portable sibling order within a single phase.