The Phase System topic explained the rules. This topic applies them, one phase at a time, to the course's DMA bench: how its tree is built and configured, how it is wired and audited at time 0, how its run window is owned, and how the simulation finally stops, cleanly or with a fatal.
Place a factory override correctly in any test, and explain exactly when "before super" matters.
Debug a failed config_db get from the path, type and field name, including the wildcard that never matches the agent itself.
Wire agents and envs with the right port, export and imp rules, and read a binding error.
Use end_of_elaboration as an audit point, knowing that any error before it stops the test.
Say who owns the run window, what the runtime phases are for, and why drivers stay in run_phase.
Explain every way a UVM simulation ends: normal completion, a fatal, the quit count, and the timeout.
Lesson | What it answers |
|---|---|
create versus build, and when a factory override is too late, measured on the bench. | |
Checked gets, the wildcard trap, and building only what the configuration selects. | |
Port, export and imp rules, handle forwarding, and binding errors. | |
What happens when end_of_elaboration starts, and how to audit the tree. | |
Who owns the run window, and what every component does inside it. | |
Reset, configure, main and shutdown, and why drivers stay in run_phase. | |
The library's base phase methods, and the silent failure when super is skipped. | |
Test selection, the timeout, the quit count, report_summarize and who calls $finish. |