connect_phase Hub: Bottom-Up TLM Wiring

Overview

connect_phase is where the pre-built component tree gets wired . Every TLM port, export, and imp is linked so transactions can flow — but no new components are created here.

The phase runs bottom-up so leaf ports exist before parents attempt to bind them into larger graphs.

Sub-lessons in this topic

1. connect-bottom-up-why - why child-before-parent ordering for wiring.

2. tlm-port-binding - seq_item_port, exports, and imp connections.

3. analysis-connect-patterns - broadcast, fanout, and subscriber wiring.

4. connect-vs-build-boundary - what belongs in connect, not build.

5. connect-phase-walkthrough - end-to-end connect timeline on a real env.

6. connect-phase-debug - null-handle and binding failure triage.

[PHASE][UVM] connect_phase position

  build_phase finished → all components exist
  connect_phase runs   → wire TLM graph only

  agent (leaf-ish)
    mon.ap ──────► sb.act_imp
    mon.ap ──────► cov.analysis_export
    drv.seq_item_port ◄── sqr.seq_item_export

TRAVERSAL: bottom-up (child connect before parent)
TIME:      zero (function phase)

function void connect_phase(uvm_phase phase);
  super.connect_phase(phase);   // always first
  // port.connect(export) or ap.connect(imp)
  // handle assignments for virtual sequencer
  // NEVER: type_id::create(), #delay, sequence.start()
endfunction

Key takeaways

• connect_phase only links existing components — it never creates them.

• Bottom-up traversal ensures child endpoints exist before parent wiring.

• Driver-sequencer, monitor-analysis, and virtual sequencer mapping are the three staples.

Common pitfalls

• Null handle at connect — build_phase did not create that component.

• Connecting port-to-port without export/imp in the chain.

• Creating components in connect_phase — breaks phase contract.

Connect-phase contract

Treat connect as pure wiring: zero time, no construction, no stimulus.

Allowed vs forbidden

[PHASE][UVM] connect_phase rules

ALLOWED:
  super.connect_phase(phase)
  port.connect(export)
  analysis_port.connect(analysis_imp)
  virtual sequencer handle assignment
  null-guard checks before connect

FORBIDDEN:
  type_id::create() / new() for uvm_components
  uvm_config_db::get for mandatory first-time setup
  #delay, wait(), @(event)
  sequence.start() / pin driving

• Mirror every conditional build branch with a connect guard.

• Call super.connect_phase before local connections.

• Use get_full_name() in fatal messages for wiring failures.

[PHASE] connect → elaboration handoff

connect_phase delivers:
  - bound driver ↔ sequencer paths
  - analysis fanout to sb/cov
  - virtual sequencer sub-sequencer map

end_of_elaboration expects:
  - stable TLM graph
  - topology ready for print_topology audit

Common pitfalls

• Wiring passive agent driver ports that were never built.

• Forgetting super.connect_phase — base connections skipped.

• Using connect to 'fix' missing build_phase components.