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Course contents

  • Start Here4
  • UVM Foundations14
  • UVM Phases & Simulation Lifecycle26
  • Factory & Configuration15
  • Transaction-Level Modeling (TLM)13
  • UVM Sequences & Stimulus21
  • UVM Agents & Protocol VIP21
  • Environment & Test Classes11
  • Checking & Coverage in UVM21
    • Scoreboard Architecture: Expected vs Actual
    • Reference Models: Predictors, DPI-C and Built-in Comparators
    • Coverage & Closure
  • UVM Register Abstraction Layer (RAL)22
  • Advanced UVM in Practice13
  • Debug & Regression10
  • Coding Practice47
  • Verification in Industry Practice10
  • Senior Prep: Architecture, Leadership and Interviews32
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‹UVM Verification
  1. Topics
  2. UVM Verification
  3. Checking & Coverage in UVM

Part 8 · Checking & Coverage · Intermediate

Checking & Coverage in UVM

How a UVM bench proves the DUT was right and measures what it tried: scoreboards, reference models and built-in comparators, and coverage closure.

  • 3topics
  • 21lessons
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    A regression of three hundred tests is green. In review, someone asks two questions. How do you know every output word was right? And how do you know the tests tried the cases that matter? The first is a checking question: a model must predict each result and a scoreboard must compare it with what the DUT really did. The second is a coverage question: a model of the test plan must record which cases ran and point at the ones that never did. A bench that cannot answer both is not finished, however green it is.

    This part answers both on the course's DMA bench. Its checking env, dma_env_check, runs the original scoreboard, a separate predictor feeding a built-in comparator, and a coverage collector side by side. On the same three random jobs, the scoreboard and the comparator agree on 14 of 14 words, and coverage still reports 8 plan holes. That gap between "everything matched" and "everything was tried" is the thread through all three topics.

    What you will be able to do

    • Design a scoreboard for the traffic your DUT really produces: in order or out of order by ID, with a check at end of test that fails when work is missing or nothing was compared.

    • Build the reference model as its own component, in SystemVerilog or in C through DPI-C, and keep it independent of the RTL it judges.

    • Choose between UVM's built-in comparators and a hand-written scoreboard, and avoid the class comparator that calls every pair a match.

    • Turn a test plan into a coverage model, read the holes it reports, and close them with directed tests or better constraints.

    The picture: one env, three topics

    Flowchart: monitors feed a scoreboard, a predictor, a built-in comparator and a coverage collector inside dma_env_check. The predictor sends expected items to the comparator, which also receives actual items. Dotted arrows link Scoreboard Architecture to the scoreboard, Reference Models to the predictor and comparator, and Coverage and Closure to the coverage collector.
    The checking env of the DMA bench, with each topic pointing at the part it teaches. Every checker listens to monitors only; none of them asks the stimulus what it intended.

    The three topics, in order

    #

    Topic

    What it covers

    1

    Scoreboard Architecture

    The expected-versus-actual model and how a scoreboard is wired into the env; in-order and ID-based out-of-order matching; and the end-of-test checks that turn a silent zero-compare run into a failure.

    2

    Reference Models

    The predictor as its own component with one virtual predict(); transaction-level versus cycle-accurate models; C models called through DPI-C; and UVM's built-in comparators, including the class comparator that passes eight wrong predictions.

    3

    Coverage & Closure

    Coverage collectors and sampling discipline, bins, crosses and plan traceability, reporting, and the closure loop, shown on the DMA's coverage model and the holes it really reports.

    Read them in order. Scoreboard Architecture sets up the compare that the other two build on. Reference Models moves the prediction out of the scoreboard so it can be swapped, written in C or fed to a built-in comparator. Coverage & Closure comes last because coverage only means something once the checks are trustworthy: a covered case that nobody checked is a case you merely watched.

    Related topics

    • Up: UVM course hub

    • Previous: Environment and Tests

    • Next: Register Model (RAL)

    PreviousNext: Scoreboard Architecture: Expected vs Actual

    Up next

    Up nextScoreboard Architecture: Expected vs Actual

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    See also

    • Start Here
    • UVM Foundations
    • UVM Phases & Simulation Lifecycle