Part 8 · Checking & Coverage · Intermediate
Predictors: uvm_reg_predictor & Bus-to-RAL
Hub — RAL mirror prediction, reg adapter, env wiring, explicit vs implicit prediction.
Overview
The uvm_reg_predictor keeps the RAL register mirror synchronized with observed bus traffic. It is the bridge between your protocol monitor and the register abstraction layer — essential for frontdoor mirror checks, multi-master register access, and any test that calls reg.mirror(UVM_CHECK) after bus activity.
Predictors are often confused with reference models. A ref model predicts transaction responses for scoreboard checking. A reg predictor updates the RAL mirror from observed register bus cycles. They serve different purposes and wire to different consumers.
Sub-topics
Predictor Role — RAL mirror vs general ref model; mirror failure walkthrough.
Reg Adapter — bus2reg and reg2bus implementation with field-by-field explanation.
Env Wiring — frontdoor and prediction paths running in parallel.
Explicit vs Implicit Prediction — auto_predict tradeoffs and double-predict trap.
Multi-Master & Debug — several monitors, backdoor predict, debug checklist.
Legend: [RAL] [UVM]
[RAL] PREDICTOR DATA PATH
monitor.ap ──► predictor.bus_in
│
▼
adapter.bus2reg(apb_item)
│
▼
uvm_reg_bus_op { kind, addr, data, byte_en, status }
│
▼
reg_map.predict(rw)
│
▼
mirror[field] = observed value
[UVM] STIMULUS PATH (parallel, not through predictor)
reg_seq.write() ──► adapter.reg2bus() ──► sequencer ──► driver ──► DUTPredictor vs scoreboard vs ref model
Component Input Output Purpose
─────────────────────────────────────────────────────────────────────────
ref model [CHECK] request txn expected response scoreboard exp stream
scoreboard [CHECK] exp + act txns UVM_ERROR value compare
predictor [RAL] observed bus txn mirror update RAL state sync
coverage [COVER] observed bus txn bin hits measurementKey takeaways
Predictor = bus-observed mirror update, not general scoreboard checking.
Frontdoor tests need both set_sequencer (stimulus) and predictor (observe).
Default to explicit prediction in integrated chip environments.