Part 8 · Checking & Coverage · Intermediate

Explicit vs Implicit Prediction

set_auto_predict, when to use uvm_reg_predictor, and avoiding double prediction.

Two prediction modes

RAL supports two ways to keep the mirror current. Implicit prediction (set_auto_predict(1)) updates the mirror inside RAL's own read/write methods — no predictor needed. Explicit prediction (set_auto_predict(0)) requires the monitor-driven predictor to call reg_map.predict() from observed bus traffic.

diagram

Legend: [RAL]

  IMPLICIT (auto_predict = 1)
  ───────────────────────────
  reg.write(data) ──► RAL updates mirror immediately ──► then drives bus
  External master write ──► mirror NOT updated (blind spot!)

  EXPLICIT (auto_predict = 0)
  ───────────────────────────
  reg.write(data) ──► drives bus ──► monitor ──► predictor ──► mirror
  External master write ──► monitor ──► predictor ──► mirror ✓
  Backdoor force ──► manual reg.predict(data) required

Configuration examples

systemverilog

// ── IMPLICIT: simple block-level test, single RAL master only ──
function void build_phase(uvm_phase phase);
  reg_model.build();
  reg_model.lock_model();
  reg_model.set_auto_predict(1);   // RAL self-updates mirror on write/read
  reg_model.default_map.set_sequencer(apb.sqr, adapter);
  // NO predictor needed
endfunction

// ── EXPLICIT: integrated chip env, multi-master, firmware updates ──
function void build_phase(uvm_phase phase);
  reg_model.build();
  reg_model.lock_model();
  reg_model.set_auto_predict(0);   // predictor owns mirror updates
  reg_model.default_map.set_sequencer(apb.sqr, adapter);
endfunction

function void connect_phase(uvm_phase phase);
  predictor.map     = reg_model.default_map;
  predictor.adapter = adapter;
  apb.mon.ap.connect(predictor.bus_in);
endfunction

Decision guide and double-predict trap

When to use each mode

diagram

Scenario                              Implicit    Explicit
──────────────────────────────────────────────────────────────────
Single RAL master, block test            ✓           ✓
CPU + DMA both write registers             ✗           ✓
Firmware updates register autonomously     ✗           ✓
DUT auto-clears status bits on read        ✗           ✓
Backdoor HDL access in same test           ✗           ✓
Need mirror to reflect actual bus data     ✗           ✓

Double prediction — mirror corruption

Enabling both auto_predict(1) AND a wired predictor causes the mirror to be updated twice per transaction — once by RAL internally, once by the predictor. The second update may overwrite with stale or duplicate data.

diagram

DOUBLE PREDICT FAILURE [RAL]

  auto_predict(1) + predictor both active:

  T0  reg.write(0xFF)
       └─ auto_predict: mirror = 0xFF  (immediate)

  T1  monitor → predictor → predict()
       └─ mirror = 0xFF again (harmless if same)

  T2  External master writes 0xAA (not via RAL)
       └─ auto_predict: mirror unchanged (still 0xFF)
       └─ predictor: mirror = 0xAA  ✓

  T3  reg.mirror(UVM_CHECK) after external write
       └─ readback = 0xAA, mirror = 0xAA → PASS

  BUT if auto_predict fires on a RAL write AND predictor
  fires on a delayed/stale monitor item:
       └─ mirror may flip between values → intermittent FAIL

Explicit: multi-master, firmware updates, DUT auto-clear bits, backdoor access.
Implicit: single RAL master only, simple block tests, no external bus masters.
Never both — double predict corrupts mirror and causes intermittent failures.

Key takeaways

Default to explicit prediction in integrated chip envs.
Implicit is acceptable only when RAL is the sole bus master.
grep for set_auto_predict and predictor in the same env — common bug.

Common pitfalls

Implicit + explicit both on — corrupted mirror, intermittent mirror check failures.
Implicit mode with firmware-driven register updates — mirror permanently stale.
Switching modes between tests without rebuilding reg_model.

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