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Course contents

  • Start Here4
  • UVM Foundations14
  • UVM Phases & Simulation Lifecycle26
  • Factory & Configuration15
  • Transaction-Level Modeling (TLM)13
  • UVM Sequences & Stimulus21
  • UVM Agents & Protocol VIP21
  • Environment & Test Classes11
  • Checking & Coverage in UVM21
    • Scoreboard Architecture: Expected vs Actual
    • Reference Models: Predictors, DPI-C and Built-in Comparators
    • Coverage & Closure
      • Designing a Coverage Model from the Spec
      • Coverage Components and Sampling
      • Bins, Illegal Bins and Ignore Bins
      • Crosses and Plan Traceability
      • Coverage Options That Change the Numbers
      • SVA cover property vs Covergroups
      • Regression Merge and the Closure Loop
      • Closing Coverage: The Holes Random Never Hits
      • Reporting and Verbosity Control
      • Code Coverage and How It Closes with Functional Coverage
  • UVM Register Abstraction Layer (RAL)22
  • Advanced UVM in Practice13
  • Debug & Regression10
  • Coding Practice47
  • Verification in Industry Practice10
  • Senior Prep: Architecture, Leadership and Interviews32
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‹Checking & Coverage in UVM
  1. Topics
  2. UVM Verification
  3. Checking & Coverage in UVM
  4. Coverage & Closure

Part 8 · Checking & Coverage · Intermediate

Coverage & Closure

Design a coverage model from the spec, sample it from monitors, score it honestly, and close the holes random stimulus never reaches.

  • 10topics
  • 10lessons
On this page

    The checking topic proved that every word the DMA moved was the right word. Every sign-off review then asks the next question: what did the tests actually exercise? A scoreboard that matched 14 words out of 14 says nothing about the zero-length job nobody ran, the error path nobody triggered, or the back-to-back beats the driver never produced. This topic builds the part of the bench that answers that question honestly, and then uses it to close the holes.

    What you will be able to do

    • Turn a spec into a testplan and a coverage model, and decide for each fact whether it belongs in a class covergroup, an interface covergroup, a cover property or register coverage.

    • Build a coverage component on analysis imps that samples observed traffic only, with sample-with-arguments covergroups and distinct instance names.

    • Choose bins, illegal bins, ignore bins, crosses and coverage options deliberately, and predict the number a report will print.

    • Merge a regression, analyse every hole by its cause, and close it with the right tool: more seeds, a constraint change, a driver fix, a directed test or a reviewed exclusion.

    The closure loop, and where each lesson sits

    Flowchart: spec to testplan to coverage model to regression to merge to hole analysis; holes lead to new tests, reviewed exclusions, or fixes to the model.
    The closure loop. The first lessons build the model (spec to covergroups), the middle ones make its numbers trustworthy, and the last ones run the loop on the DMA's real holes.

    Every arrow in the loop is a place where teams fool themselves: a model that samples intent instead of behaviour, a merge that averages instead of unions, a hole "closed" by an ignore bin. The lessons follow the loop in order and use the course bench's dma_coverage component and its real logs throughout.

    Lessons in order

    #

    Lesson

    The question it answers

    1

    Designing a Coverage Model from the Spec

    What should be covered, and where is each fact sampled?

    2

    Coverage Components and Sampling

    How does a coverage component listen to monitors and sample only what the DUT did?

    3

    Bins, Illegal Bins and Ignore Bins

    What makes a value counted, ignored or an error?

    4

    Crosses and Plan Traceability

    Which combinations matter, and how does each plan row map to the model?

    5

    Coverage Options That Change the Numbers

    Why do two reports of the same hits print different percentages?

    6

    SVA cover property vs Covergroups

    When is a fact temporal, and where does that coverage live?

    7

    Regression Merge and the Closure Loop

    How do per-test results become one sign-off number?

    8

    Closing Coverage: The Holes Random Never Hits

    Why did the DMA's random test leave 8 holes, and how was each one closed?

    9

    Reporting and Verbosity Control

    What decides what the log says and whether a test fails?

    10

    Code Coverage and How It Closes with Functional Coverage

    What does code coverage add, and how do the two kinds of coverage close together?

    Note

    On this course's simulator (Verilator with the open-source UVM library), covergroups compile but their coverpoints are ignored, so every covergroup percentage prints 0.0%. The bench therefore also keeps a named plan-item tally, and that tally is the coverage evidence in this topic's logs. On a commercial simulator such as Riviera-PRO the covergroup percentages are real.

    Related topics

    • Up: Scoreboards, Models & Coverage

    • Scoreboard architecture

    • The DMA you will verify

    PreviousNext: Designing a Coverage Model from the Spec

    Up next

    Up nextDesigning a Coverage Model from the Spec

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    See also

    • Scoreboard Architecture: Expected vs Actual
    • Reference Models: Predictors, DPI-C and Built-in Comparators