Bins, illegal_bins, and ignore_bins

Why explicit bins matter

SystemVerilog auto-bins generate one bin per unique value. On an 8-bit field that is 256 bins; on a 32-bit address field it is billions. Explicit bins define the buckets that matter for your verification plan — typically 3–10 bins per coverpoint, not thousands.

Legend: [COVER]

  BIN TYPES

  bins        — legal values you want to track and close
  illegal_bins — protocol violations; hit → simulation error
  ignore_bins  — legal but irrelevant; excluded from coverage denominator

  cp_state: coverpoint tr.state {
    bins idle   = {IDLE};       ← must cover
    bins setup  = {SETUP};      ← must cover
    bins access = {ACCESS};    ← must cover
    illegal_bins bad = {3'b111}; ← protocol violation → UVM_ERROR
    ignore_bins  rsv = {3'b110}; ← reserved encoding, not in plan
  }

Bin design patterns

covergroup cg with function sample(bus_txn tr);

  // Named bins matching plan rows
  cp_state: coverpoint tr.state {
    bins idle   = {IDLE};
    bins setup  = {SETUP};
    bins access = {ACCESS};
    illegal_bins bad = {3'b111};   // protocol violation
    ignore_bins  rsv = {3'b110};   // reserved, not in plan
  }

  // Range bins for numeric fields
  cp_len: coverpoint tr.len {
    bins single = {1};
    bins small  = {[2:4]};
    bins large  = {[5:16]};
  }

  // Wildcard bins for sparse address sets
  cp_addr: coverpoint tr.addr {
    bins low  = {[0:255]};
    bins high = {[65536:$]};
    wildcard bins aligned = {0, 4, 8, 16};
  }

  // Transition bins for FSM sequences
  cp_fsm: coverpoint tr.state {
    bins idle_to_setup = (IDLE => SETUP);
    bins setup_to_acc  = (SETUP => ACCESS);
    bins acc_to_idle   = (ACCESS => IDLE);
  }

endgroup

Bin design rules

When to use each bin type

• bins — every value or range your verification plan requires; name matches plan feature ID.

• illegal_bins — encoding that violates the protocol spec; triggers error on hit (coverage + check combined).

• ignore_bins — legal values outside test scope; shrinks denominator without affecting closure goal.

• wildcard bins — sparse value sets (aligned addresses, power-of-two sizes) without listing every value.

• transition bins — FSM arc coverage; (STATE_A => STATE_B) tracks the sequence, not just the state.

BIN EXPLOSION EXAMPLE [COVER]

  cp_data: coverpoint tr.data;   // NO explicit bins
  → 2^32 auto-bins → uncloseable, sim slowdown, useless report

  cp_data: coverpoint tr.data {
    bins zero = {0};
    bins all1 = {32'hFFFF_FFFF};
    bins other = default;         // one catch-all bin
  }
  → 3 bins → closeable, meaningful

Key takeaways

• Name bins to match verification-plan rows — enables traceability.

• Never use default auto-bins on wide fields — bin explosion.

• illegal_bins combines protocol checking with coverage in one coverpoint.

Common pitfalls

• Auto-bins on 32-bit fields — billions of bins, sim never closes.

• ignore_bins on values the plan requires — false closure.

• Transition bins without sampling every cycle — miss multi-step sequences.