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Course contents

  • Start Here4
  • UVM Foundations14
    • What Is UVM?
    • Testbench Architecture and Environment Composition
  • UVM Phases & Simulation Lifecycle26
  • Factory & Configuration15
  • Transaction-Level Modeling (TLM)13
  • UVM Sequences & Stimulus21
  • UVM Agents & Protocol VIP21
  • Environment & Test Classes11
  • Checking & Coverage in UVM21
  • UVM Register Abstraction Layer (RAL)22
  • Advanced UVM in Practice13
  • Debug & Regression10
  • Coding Practice47
  • Verification in Industry Practice10
  • Senior Prep: Architecture, Leadership and Interviews32
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←UVM Verification
  1. Topics
  2. UVM Verification
  3. UVM Foundations
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    Part 1 of 15Part 1 of 15/FoundationsIntermediate

    UVM Foundations

    The mental model of UVM and the complete DMA testbench: what UVM standardizes, components versus objects, item utilities, testplans, and how a bench is layered and reused.

    • 2topics
    • 14lessons

    SoC teams tell the same story again and again: a chip team has to rewrite a dozen block-level agents because none of them can run passive, since each one assumed it owned its bus, and the rewrite costs more than the original block verification. Foundations exists so your benches never need that rewrite. It builds the mental model of UVM, then one complete, running testbench for the course's DMA, and shows why its structure survives the move from block to chip.

    What you will be able to do

    • Explain why UVM exists, what it standardizes and what your project must still build.

    • Pick uvm_component or uvm_object for any class, and write an item's copy, compare and print methods.

    • Turn a spec feature into a testplan row with stimulus, a check and coverage.

    • Build, run and break a complete UVM bench, and explain every part of it.

    • Draw the four layers, reuse an agent active or passive, wire an env, coordinate agents, and debug a composed bench in a fixed order.

    Learning path: the What Is UVM topic ends at the first testbench, which leads into the Testbench Architecture topic.
    Two topics. The first ends with the complete DMA bench running; the second explains why it is built that way and how it scales.

    The two topics

    Topic

    Lessons

    What it covers

    Time

    What Is UVM?

    7

    Why UVM exists and where its edges are, the component-object fork, item utilities, the testplan triangle, and the complete DMA bench.

    about 3 h

    Testbench Architecture and Environment Composition

    5

    The four layers, active and passive agents, env wiring, coordinating agents, and composition debug.

    about 2 h

    New to the course? Read Start here first, especially The DMA you will verify: every lesson in this part tests that design.

    Check yourself Why is a sequence item a uvm_object rather than a uvm_component?

    Items are transient data, created per transfer by the thousand, with no fixed place in the tree and no phases. Components are the persistent tree that items flow through. Components vs objects covers the fork and what follows from it.

    Typical questions from this part: why UVM, and when you would not use it; uvm_object versus uvm_component; field macros versus do_copy and do_compare; how you know verification is done; walk me through a testbench you built; and what changes when a block bench goes into a chip.

    Related topics

    • Up: UVM course hub

    • Before: Start here

    • Next: Phases

    PreviousNext: What Is UVM?

    Up next

    Up nextWhat Is UVM?

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    See also

    • Start Here
    • UVM Phases & Simulation Lifecycle
    • Factory & Configuration