UVM Foundations

What this section covers

Before you write a single uvm_agent, you need a stable mental model of what UVM actually is, what it standardizes for you, and what stays your responsibility. This section builds that model from the ground up so the rest of the course — phases, factory, sequences, RAL — lands on solid footing.

UVM is a class library plus a methodology . The library is roughly 350 SystemVerilog classes shipped by Accellera; the methodology is the set of conventions that tell you how to assemble those classes into a testbench that other people can read, reuse, and extend. Neither half is a simulator, a language, or an EDA tool — UVM runs on top of any IEEE 1800 SystemVerilog simulator.

Lessons in this section

1. What Is UVM? — history, goals, and the IEEE 1800.2 standard.

2. The UVM Class Library Map — the base-class tree and how to navigate it.

3. Components vs Objects — persistent phased tree vs transient data.

4. Layered Testbench Architecture — test, env, agent, and DUT layers.

5. Verification Plan Basics — tracing TB structure to plan features.

6. Stimulus, Check & Coverage — the three legs of modern DV.

7. Your First UVM Testbench — an end-to-end walkthrough that ties it together.

The big picture in one diagram

UVM TESTBENCH AT A GLANCE (top = test intent, bottom = pins)

  uvm_test            chooses scenario, sets overrides, starts top sequence
     |
  uvm_env             owns reusable infrastructure (agents, scoreboard, RAL)
     |
  uvm_agent           one protocol interface: driver + sequencer + monitor
     |   \
  driver  monitor     driver pushes pins; monitor observes pins
     |        \
  virtual interface    bridge between class-based TB and the HDL DUT
     |
  +----------------+
  |      DUT       |   the RTL under test
  +----------------+

  (objects — sequence_item, sequence, config — flow THROUGH this tree)

Every later topic is an elaboration of this picture: phases decide WHEN each box runs, the factory decides WHICH class fills each box, config_db decides WHAT each box is told, and sequences decide what traffic flows through.

Key takeaways

• UVM is a library + methodology, not a tool or a language extension.

• A UVM testbench is a static tree of components with transient objects flowing through it.

• Master the foundations and the advanced topics become variations on one diagram.