Every UVM interview has a whiteboard moment: draw the testbench. Anyone can draw boxes. What the interviewer is really checking is whether you know which box changes when the requirements change: a new scenario, a new protocol, the same block inside a chip. This topic answers that for the DMA bench, one boundary at a time.
Draw the four layers of a UVM testbench and say what crosses each boundary.
Build an agent that works active at block level and passive at chip level without a code change.
Wire an env so build creates and connect connects, with analysis traffic fanning out to every checker.
Coordinate several agents into one scenario, with or without a virtual sequencer.
Debug a composition problem in a fixed order instead of by guesswork.
Layer | Owns | In the DMA bench |
|---|---|---|
Test | The scenario, overrides, the top-level stimulus |
|
Env | Agents, checkers, coverage, the register model |
|
Agent | Driver, sequencer and monitor for one interface |
|
Interface | The pins, reached through a virtual interface |
|
Lesson | What it covers |
|---|---|
What each layer owns, what crosses each boundary, and how virtual interfaces reach the right components. | |
Active and passive builds, the agent's public analysis port, and block-to-chip reuse. | |
Build creates, connect wires, analysis fan-out, and the two ways to hand config down. | |
Turning a DMA job into one virtual sequence, and the ordering bug that coordination prevents. | |
The same env at block and subsystem level, and a fixed triage order with UVM's own debug calls. |