In the DMA bench, no test touches a pin. The tests start sequences, which create transaction objects, and the drivers turn each one into signal activity at the right clock edges. A register write is an apb_rw_seq; a packet is an axis_pkt_seq; a whole job with polling and an interrupt handler is a virtual sequence, dma_vseq, that runs both kinds side by side. This part of the course explains every layer of that, from the single item to the multi-agent scenario.
Design sequence items and constraints that keep stimulus legal and let each test aim at its corner, without editing the agent.
Draw the start_item / finish_item / get_next_item / item_done handshake and write drivers, in order or pipelined, that honour it.
Explain what start() does, how the sequencer arbitrates, how responses come back, and how to stop stimulus cleanly around a reset.
Coordinate several agents from one virtual sequence, with or without a virtual sequencer, and take exclusive control of a sequencer when an interrupt arrives.
Topic | Lessons | What it covers |
|---|---|---|
6 | What belongs in an item, constraints and | |
6 | What | |
9 | Coordinating the register, stream and interrupt agents from one scenario: virtual sequencers and the alternative of handles set by the test, |
Two related lessons live in the Factory & Configuration part and are not repeated here: Configuring sequences (knobs, per-path settings and default sequences) and Overriding items and sequences (type and instance overrides aimed at stimulus).