Virtual Sequences and Coordination · UVM

Part 5 · Sequences · Intermediate

9topics
9lessons

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One DMA job touches three interfaces: registers over APB, data over AXI-Stream, and an interrupt line. A single-agent sequence can drive one of them. Something has to own the story across all three: program the registers, stream the data, notice the interrupt, clear it, and do it again with different numbers. That something is a virtual sequence, and this topic is about writing one well.

What you will be able to do

Explain why cross-agent ordering belongs in a virtual sequence and not in the test, and keep tests thin.
Wire a virtual sequencer, declare p_sequencer, and explain the DCLPSQ fatal you get when the types do not match.
Run a virtual sequence with no virtual sequencer at all, the way the bench's dma_vseq does, and say when that is the better choice.
Compose sequences from sub-sequences, run a sequence library, and predict exactly which sequence gets the sequencer under lock() and grab().
Build a translator sequence that turns upper-layer items into bus traffic, and a responder sequence that answers the DUT.

How the pieces fit on the bench

Flowchart: dma_vseq_test starts dma_vseq, which starts three register writes, a poller and an interrupt handler on the APB sequencer and a packet sequence on the stream sequencer.

The bench's virtual sequence: one class orders the register writes, then runs polling, data and the interrupt handler in parallel. Three sequences share the APB sequencer, so arbitration and grab decide who goes next.

Read the left half as who decides the order and the right half as who decides the next bus access. The virtual sequence owns the first question. The sequencer's arbitration (Inside the Sequencer), and lock() or grab(), own the second. Most bugs in this topic come from mixing the two up.

The lessons, in order

Lesson	What it answers
The Coordination Problem	Why a DMA job needs one owner across three interfaces, and how that keeps tests thin.
Virtual Sequencer Wiring	The handle-bundle component, why handles are assigned in connect_phase, and null-handle defence.
Declaring p_sequencer	What the macro expands to, the `DCLPSQ` fatal, and what the parent argument really controls.
Scenario Patterns and Placement	Fork shapes, stopping a background sequence cleanly, layered vseqs, and who owns which sequence.
Sub-sequences and Sequence Libraries	Composing sequences with the parent argument, and libraries that let the seed pick the sequence.
Virtual Sequences Without a Virtual Sequencer	The bench's `dma_vseq`: handles from the test, `start(null)`, trade-offs, a base vseq class.
lock vs grab: Who Gets the Sequencer	Queue position, children of the holder, nested locks, deadlocks and killed lock holders, with a real log.
Protocol Layering with Translator Sequences	DMA jobs as upper-layer items, translated into APB writes and stream beats, and rebuilt by a monitor.
Reactive (Slave) Sequences	A responder that answers what a monitor saw: random TREADY backpressure on the DMA's output.

Before you start, make sure the handshake between a sequence and a driver is solid: the driver loop is assumed throughout. Start with: The Coordination Problem.

Up nextThe Coordination Problem

Practice this lesson Report an error

What you will be able to do

Explain why cross-agent ordering belongs in a virtual sequence and not in the test, and keep tests thin.

Wire a virtual sequencer, declare p_sequencer, and explain the DCLPSQ fatal you get when the types do not match.

Run a virtual sequence with no virtual sequencer at all, the way the bench's dma_vseq does, and say when that is the better choice.

Compose sequences from sub-sequences, run a sequence library, and predict exactly which sequence gets the sequencer under lock() and grab().

Build a translator sequence that turns upper-layer items into bus traffic, and a responder sequence that answers the DUT.

How the pieces fit on the bench

Flowchart: dma_vseq_test starts dma_vseq, which starts three register writes, a poller and an interrupt handler on the APB sequencer and a packet sequence on the stream sequencer.

The lessons, in order

Lesson	What it answers
The Coordination Problem	Why a DMA job needs one owner across three interfaces, and how that keeps tests thin.
Virtual Sequencer Wiring	The handle-bundle component, why handles are assigned in connect_phase, and null-handle defence.
Declaring p_sequencer	What the macro expands to, the `DCLPSQ` fatal, and what the parent argument really controls.
Scenario Patterns and Placement	Fork shapes, stopping a background sequence cleanly, layered vseqs, and who owns which sequence.
Sub-sequences and Sequence Libraries	Composing sequences with the parent argument, and libraries that let the seed pick the sequence.
Virtual Sequences Without a Virtual Sequencer	The bench's `dma_vseq`: handles from the test, `start(null)`, trade-offs, a base vseq class.
lock vs grab: Who Gets the Sequencer	Queue position, children of the holder, nested locks, deadlocks and killed lock holders, with a real log.
Protocol Layering with Translator Sequences	DMA jobs as upper-layer items, translated into APB writes and stream beats, and rebuilt by a monitor.
Reactive (Slave) Sequences	A responder that answers what a monitor saw: random TREADY backpressure on the DMA's output.

Before you start, make sure the handshake between a sequence and a driver is solid: the driver loop is assumed throughout. Start with: The Coordination Problem.