UVM Register Abstraction Layer (RAL)

Manipulate registers by name, not bus packets

The Register Abstraction Layer lets a test write ral.ctrl.enable.set(1); ral.ctrl.update(status); instead of hand-assembling a bus write to address 0x40 with bit 3 set. The model abstracts the address map, field access policies, and reset values — register tests survive protocol and address-map changes.

RAL topic map

Legend: [UVM] [RAL] [BUS] [HDL]

┌─────────────────────────────────────────────────────────────────────────┐
│  REGISTER MODEL (RAL) — topic map (each hub has 5–6 sub-lessons)        │
├─────────────────────────────────────────────────────────────────────────┤
│  1. OVERVIEW [RAL]     block tree │ reg_map │ generated vs hand │ lock  │
│  2. FIELDS [RAL]       policies │ configure │ volatile │ reset │ hw_rst │
│  3. ADAPTERS [BUS]     reg2bus │ bus2reg │ built-in seqs │ mem access   │
│  4. MIRROR [RAL]       desired │ mirrored │ predict │ mirror(UVM_CHECK) │
│  5. ACCESS PATHS [HDL] frontdoor bus │ backdoor HDL │ access_seq        │
│  6. INTEGRATION [UVM]  env wiring │ predictor │ config_db │ debug        │
└─────────────────────────────────────────────────────────────────────────┘

End-to-end data flow

[TEST]  ral.ctrl.enable.set(1); ral.ctrl.update(status)
              │
              ▼
[RAL]   uvm_reg_map + uvm_reg_adapter
              │
    ┌─────────┴─────────┐
    ▼                   ▼
[BUS] FRONTDOOR         [HDL] BACKDOOR
sequencer→driver→DUT    uvm_hdl_read/deposit
    │                   │
    ▼                   │
monitor→predictor→mirror (keeps model in sync)

Topics and sub-topics

1. RAL Overview — 6 sub-lessons on uvm_reg_block hierarchy, maps, generation, and lock_model.

2. Registers, Fields & Access Policies — 6 sub-lessons on policies, configure(), volatile fields, and reset verification.

3. Bus Adapters & Built-in Sequences — 6 sub-lessons on reg2bus/bus2reg and bring-up sequences.

4. Mirror & Predict — 6 sub-lessons on desired/mirrored values, predict(), and drift debug.

5. Frontdoor vs Backdoor Access — 6 sub-lessons on bus path vs HDL path and when to use each.

6. RAL Integration in the Environment — 6 sub-lessons on env wiring, predictor, and config_db sharing.

Key takeaways

• RAL is a by-name register API decoupled from the bus protocol.

• Adapter bridges abstract ops to bus items; predictor keeps the mirror aligned.

• Frontdoor proves the bus path; backdoor is fast setup — cross-check with access_seq.

How to use this section

Open a topic hub for an overview and diagram, then drill into sub-lessons for theory, walkthroughs, and code. Run built-in sequences (hw_reset, bit_bash) before custom register tests.

• Generated models from IP-XACT/SystemRDL — extend via callbacks, never edit generated code.

• set_auto_predict(0) + explicit predictor is the robust default for frontdoor flows.

• Mirror checks only work when the predictor models every path that changes registers.