This topic builds the register model of the course's DMA, dma_reg_block in dma_ral_tb.sv, and follows one access through it. By the end you can read any UVM register model, generated or hand-written, and say where each value it holds came from.
Say what problem a register model solves, and keep desired, mirrored and DUT values apart.
Read and write field configure() calls, and pick the access policy, volatility and reset for each DMA bit.
Turn a register name into a bus address and back, and say what map endianness does and does not do.
Compose two DMA models into one subsystem model with add_submap, and catch an overlapping base.
Put build(), configure() and lock_model() in the right order, and keep a generated model as the one source of truth.
Trace one frontdoor access from the test to the mirror, and explain why the mirror can lag the bus.
# | Lesson | What it covers |
|---|---|---|
1 | Name-based access instead of hand-built bus writes; desired, mirrored and DUT values; the LEN write the model believed and the DMA ignored. Start here. | |
2 | The DMA model as a tree; every | |
3 |
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4 | Two DMA models under one subsystem block, HDL paths across levels, and a base-address slip that only warns. | |
5 | The build order, what | |
6 | One STATUS read from the test to the mirror, on the real log, including the moment the mirror lags the bus. |
The first lesson is about why; lessons 2 to 5 build the model; lesson 6 runs it. The access API, the adapter contract and the prediction modes each have their own lessons in Register Access.