Frontdoor vs Backdoor Access

Overview

RAL offers two access paths to the same register model: frontdoor through the real bus stack and backdoor through direct HDL visibility. Good verification strategy does not pick one forever; it composes both paths intentionally.

Frontdoor validates protocol behavior, address decode, adapter mapping, and response timing. Backdoor gives fast setup and introspection, ideal for preconditioning state and debug snapshots with minimal simulation overhead.

Lessons in this topic

1. Frontdoor Bus Path - full sequencer to driver timeline, response handling, and predictor synchronization.

2. Backdoor HDL Path - add_hdl_path_slice modeling plus uvm_hdl_read and uvm_hdl_deposit usage.

3. When to Use Each - decision table and scenario-driven choice rules.

4. Access Sequence Cross-Check - uvm_reg_access_seq walkthrough and triage patterns.

5. Backdoor Permissions - DPI bridge requirements, visibility constraints, and simulator switch hygiene.

6. Mixed Access Patterns - practical flow using backdoor initialization and frontdoor feature proof.

Path map

[RAL][BUS][HDL] register access map

  test intent
      |
      v
  ral.reg.write/read(...)
      |
      +--> path = UVM_FRONTDOOR -------------------------------+
      |        |                                               |
      |        v                                               |
      |   [RAL] reg_map + adapter                             |
      |        |                                               |
      |        v                                               |
      |   [BUS] sequencer -> driver -> DUT bus pins           |
      |        |                                               |
      |        v                                               |
      |   monitor -> predictor -> mirror update               |
      |                                                        |
      +--> path = UVM_BACKDOOR --------------------------------+
               |
               v
          [HDL] add_hdl_path(_slice) resolution
               |
               v
          uvm_hdl_read / uvm_hdl_deposit
               |
               v
          mirror policy update and compare flow

[UVM] verification intent split

  Need bus/protocol confidence?
    -> frontdoor first

  Need rapid state setup or direct peek?
    -> backdoor first

  Need signoff-grade consistency?
    -> run both and cross-check using uvm_reg_access_seq

Key takeaways

• Frontdoor proves integration correctness across adapter, bus, and DUT decode.

• Backdoor is high-speed and high-observability but bypasses bus behavior.

• The strongest RAL strategy combines both paths with explicit cross-check sequences.

Common pitfalls

• Backdoor-only regressions that never exercise real bus behavior.

• Frontdoor-only bring-up that wastes cycles on massive initialization traffic.

• Assuming mirror coherence without defining prediction policy across mixed paths.