Environment & Test Classes

Env integrates; test orchestrates

The environment is reusable plumbing — agents, scoreboards, coverage, RAL, virtual sequencer. The test is scenario policy — configuration, factory overrides, virtual sequences, and end-of-test control. That boundary is what lets a testbench scale to hundreds of tests.

Env & test topic map

Legend: [UVM] [ENV] [TEST] [CHECK]

┌─────────────────────────────────────────────────────────────────────────┐
│  ENVIRONMENT & TEST — topic map (each hub has 5–6 sub-lessons)          │
├─────────────────────────────────────────────────────────────────────────┤
│  1. ENV COMPOSITION [ENV]  multi-agent │ connect_phase │ hierarchy       │
│  2. SCOREBOARD/COV [CHECK] analysis wiring │ dual-stream │ coverage sub  │
│  3. TEST BASE [TEST]       base_test │ inheritance │ factory overrides    │
│  4. CONFIG DIST [UVM]      config_db from test │ build_phase push         │
│  5. VIRTUAL SQR [ENV]      v_sqr in env │ agent sqr handles │ vseq start   │
│  6. PLUSARGS [TEST]        +UVM_TESTNAME │ cmdline_processor │ matrix     │
│  7. END TEST [UVM]         objections │ drain_time │ global timeout       │
│  8. TOP MODULE [UVM]       interfaces │ config_db vif │ run_test()       │
└─────────────────────────────────────────────────────────────────────────┘

The stack in one diagram

HDL top → run_test() → uvm_test (base_test → my_test)
                              └─ uvm_env [ENV]
                                   ├─ agents (active/passive)
                                   ├─ scoreboard + coverage [CHECK]
                                   ├─ reg model (RAL)
                                   └─ virtual_sequencer
                                        ▲
              test.run_phase: vseq.start(env.v_sqr)

Topics and sub-topics

1. uvm_env Composition — 6 sub-lessons on multi-agent integration and connect_phase.

2. Scoreboard & Coverage in the Env — 6 sub-lessons on analysis port wiring.

3. Test Base Classes — 6 sub-lessons on base_test and scenario inheritance.

4. Distributing Configuration — 6 sub-lessons on pushing config from the test.

5. Virtual Sequencer in the Env — 6 sub-lessons on env-owned orchestration.

6. Plusargs & Test Selection — 6 sub-lessons on +UVM_TESTNAME and cmdline.

7. Ending the Test — 6 sub-lessons on objections, drain_time, and timeouts.

8. Top Module & UVM Startup — 6 sub-lessons on interfaces and run_test().

Key takeaways

• The env integrates reusable components; the test selects scenario and policy.

• An env should compile and run unchanged across dozens of tests.

• The HDL top module is the thin bridge that sets interfaces and calls run_test().

How to use this section

Open a topic hub for an overview, then drill into sub-lessons. Keep env wiring in connect_phase; keep scenario logic in the test run_phase.

• Never put stimulus policy inside the env — that belongs in tests and virtual sequences.

• Virtual sequencer lives in the env; virtual sequences live in tests or a sequence library.

• End-of-test policy (objections, timeout) should be consistent across all tests via base_test.