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Course contents

  • Start Here4
  • UVM Foundations14
  • UVM Phases & Simulation Lifecycle26
  • Factory & Configuration15
  • Transaction-Level Modeling (TLM)13
  • UVM Sequences & Stimulus21
  • UVM Agents & Protocol VIP21
  • Environment & Test Classes11
    • Environment Architecture
    • Tests: Base Classes, Selection and Startup
  • Checking & Coverage in UVM21
  • UVM Register Abstraction Layer (RAL)22
  • Advanced UVM in Practice13
  • Debug & Regression10
  • Coding Practice47
  • Verification in Industry Practice10
  • Senior Prep: Architecture, Leadership and Interviews32
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←UVM Verification
  1. Topics
  2. UVM Verification
  3. Environment & Test Classes
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    Part 7 of 15Part 7 of 15/Environment & TestsIntermediate

    Environment & Test Classes

    How the DMA bench's environment and tests are designed: env config objects, reusing the block env in a two-DMA subsystem, third-party VIP, virtual sequencer placement, the base test and its nine scenario tests, test selection and test-library design.

    • 2topics
    • 11lessons

    Agents know one interface each. Above them sit two layers that decide whether a testbench scales: the environment, which assembles agents and checkers into something reusable, and the tests, which turn that assembly into scenarios. On the DMA bench, one 30-line environment is reused twice, unchanged, to verify a two-DMA chain, and one base test supports nine scenarios that differ by a few lines each. This part explains the design decisions behind both, and the mistakes that make benches impossible to reuse.

    What you will be able to do

    • Design an environment with a config object that works with or without a test-provided config, and decide what belongs in env config, agent config and the test.

    • Reuse a block environment inside a subsystem environment unchanged, with passive agents on internal buses and an end-to-end checker on top.

    • Integrate third-party VIP behind an adapter, a config map and a message policy, and choose where the virtual sequencer lives at each level.

    • Write a base test that every scenario can rely on, express each scenario as one kind of change, register factory overrides from tests, and put end-of-test policy in one place.

    • Select tests and knobs from the command line, write a top module the next level can replace, and grow a test library without copy-paste.

    Read the environment first, then the tests

    Learning path: Environment Architecture first, then the Tests topic's base test and scenarios, then selection, the top module and test-library design.
    Recommended order. Tests only make sense once you know what the environment promises them, so start with Environment Architecture, which is first in the menu.

    The topics

    Topic

    Lessons

    What it covers

    Environment Architecture

    4

    dma_env and env config objects (dma_subsys_cfg), vertical reuse in the two-DMA subsystem bench, wrapping third-party VIP, and where the virtual sequencer lives. Start here.

    Tests: Base Classes, Selection and Startup

    7

    dma_base_test and its helpers, the nine derived tests as scenarios, factory overrides from tests, shared end-of-test policy, +UVM_TESTNAME and plusargs, the top module, and designing a test library.

    Some neighbouring material is taught elsewhere and only linked from here: run_test and timeouts (how a run ends), Command-line overrides (factory and config plusargs), and the two virtual-sequence lessons, Virtual Sequencer Wiring and Virtual Sequences Without a Virtual Sequencer.

    A quick test of an environment's design: could the next level of integration instantiate it unchanged? If the answer needs an edit inside the env, a decision that belongs in configuration has been hard-coded.

    Typical questions from this part: what goes in an env config object and how it reaches the agents; how you reuse a block env at subsystem level; how you integrate a vendor VIP; whether you need a virtual sequencer; what your base test owns; type versus instance overrides; how +UVM_TESTNAME interacts with run_test; and how you would restructure a bloated regression.

    Related topics

    • Up: UVM course hub

    • Previous: Agents

    • Next: Checking

    PreviousNext: Environment Architecture

    Up next

    Up nextEnvironment Architecture

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    See also

    • Start Here
    • UVM Foundations
    • UVM Phases & Simulation Lifecycle