Part 8 · Checking & Coverage · Intermediate
Predictor Role: RAL Mirror Synchronization
Why frontdoor tests need explicit prediction and how predict() updates the mirror.
What the RAL mirror is
Every uvm_reg and uvm_reg_field in the RAL model carries a software-side mirror — a copy of what the register block should contain. Tests read and write this mirror via RAL API calls. The DUT holds the real hardware register. The mirror is only accurate when prediction keeps it in sync.
Frontdoor access — RAL sequence drives the bus; DUT register updates on the wire.
Backdoor access — HDL path or force directly updates DUT; mirror must be manually predicted.
Mirror check — reg.mirror(UVM_CHECK) reads DUT via bus and compares to mirror.
Without predictor — mirror check fails
After a frontdoor reg.write(), the DUT register updates but the RAL mirror may still hold the old value unless predict() runs from observed bus traffic. This produces a false failure — the DUT is correct, but the mirror is stale.
MIRROR FAILURE EXAMPLE [RAL]
Step 1: reg_model.ctrl_reg.write(status, 32'h0000_00FF);
RAL issues frontdoor write via sequencer → driver → DUT
Step 2: DUT register ctrl_reg = 32'h0000_00FF ✓ (hardware updated)
Step 3: RAL mirror ctrl_reg.mirror = 32'h0000_0000 ✗ (never predicted)
Step 4: reg_model.ctrl_reg.mirror(UVM_CHECK);
Frontdoor readback = 32'h0000_00FF
Mirror = 32'h0000_0000
Result: UVM_ERROR — MIRROR MISMATCH (false failure!)Timeline walkthrough
Time ─────────────────────────────────────────────────────────────►
T0 reg.write(0xFF) called
│
├─ RAL mirror still 0x00 (no auto_predict)
└─ reg2bus → driver starts APB write cycle
T1 Monitor observes PSEL, PWRITE, PWDATA=0xFF on bus
│
└─ (no predictor) → mirror unchanged
T2 DUT register latches 0xFF
│
└─ mirror still 0x00
T3 reg.mirror(UVM_CHECK) issues frontdoor read
│
├─ readback from DUT = 0xFF
├─ mirror = 0x00
└─ COMPARE FAIL → UVM_ERRORWith predictor — mirror stays synchronized
Time ─────────────────────────────────────────────────────────────►
T0 reg.write(0xFF) → driver → DUT
T1 Monitor observes write cycle
│
└─ predictor.bus_in receives apb_item
│
▼
adapter.bus2reg() → { kind=WRITE, addr, data=0xFF }
│
▼
reg_map.predict(rw) → mirror = 0xFF ✓
T2 reg.mirror(UVM_CHECK)
│
├─ readback = 0xFF
├─ mirror = 0xFF
└─ COMPARE PASS ✓Key takeaways
Explicit predictor required for reliable frontdoor mirror checks.
Predictor watches monitor — updates mirror from what DUT actually saw.
Distinct from scoreboard — predictor updates RAL state, not transaction compare.
Common pitfalls
Assuming reg.write() updates mirror — only true with auto_predict(1).
Mirror check without predictor wiring — most common RAL false-failure cause.
Using predictor output for scoreboard checking — wrong abstraction level.