Every UVM test has to answer one question the simulator cannot answer for it: is the work finished, or is the bench just quiet for a moment? Objections are UVM's answer. This topic takes you from the counter inside one phase to the end-of-test design of a whole bench, using the course DMA bench and its real logs throughout.
Read an objection trace and say, from the counts alone, who is holding the run phase open.
State the counting rules interviewers probe: drop without raise, raise in a function phase, a test that never raises.
Size a drain time from measured latency, and know when drain time is the wrong tool.
Write a phase_ready_to_end hold that cannot pass with a word missing.
Choose an end-of-test mechanism for a bench and defend the choice, including at SoC scale.
Lesson | What it answers |
|---|---|
Where the counts live, how one raise reaches uvm_top, and a runnable model of the counter. | |
Pairing, OBJTN_ZERO, NULL_OBJECTION, sequences as raisers, and the test that ends at time 0. | |
The grace period after the last drop: how it stacks, how a raise cancels it, how to size it. | |
The last-chance hold, built from the bench's end-of-test scoreboard and a real false-pass bug. | |
Five mechanisms compared, their failure modes, and how to choose one per bench. | |
Per-transaction cost, propagate mode, objection callbacks, and count versus total. |
When a test hangs instead of ending, go to Objection triage and hang forensics in the next topic.