Part 2 · Phases & Lifecycle · Intermediate

Traversal Order Rules: Top-Down vs Bottom-Up

Why build and start_of_simulation are top-down, why connect and cleanup phases are bottom-up, and what ordering is — and is not — guaranteed.

The two traversal directions

For each phase the scheduler picks top-down (parent before children) or bottom-up (children before parent). The choice follows dependency direction.

Top-down phases

  • build_phase — parent must exist to create children.

  • start_of_simulation_phase — parents announce before children.

  • final_phase — parents finalize shared resources top-down.

Bottom-up phases

  • connect_phase — leaf ports ready before parent wiring.

  • end_of_elaboration_phase — children self-check before parent aggregates.

  • extract_phase, check_phase, report_phase — children settle before parent summary.

diagram
[UVM][PHASE] dependency rule

if parent needs children to exist first:
  -> top-down (build, start_of_sim)

if parent needs children to finish first:
  -> bottom-up (connect, extract, check, report)

Key takeaways

  • Direction is per-phase, not per-component choice.

  • Top-down = parent enables children; bottom-up = children enable parent.

  • Only cross-phase ordering is a portable guarantee.

Common pitfalls

  • Relying on driver build before monitor build within same agent.

  • Parent-level connect expecting children not yet built — wrong phase, not wrong direction.

  • Assuming report_phase on env runs before agent report — it runs after (bottom-up).


Worked traversal on a deep tree

diagram
component tree:
  test
   └ env
      └ axi_agent
         ├ driver
         ├ monitor
         └ sequencer

build_phase order (TD):
  1 test
  2 env
  3 axi_agent
  4 driver, 5 monitor, 6 sequencer  (sibling order NOT guaranteed)

connect_phase order (BU):
  1 driver, 2 monitor, 3 sequencer  (sibling order NOT guaranteed)
  4 axi_agent
  5 env
  6 test
systemverilog
function void end_of_elaboration_phase(uvm_phase phase);
  super.end_of_elaboration_phase(phase);
  if (get_full_name() == "uvm_test_top.env")
    uvm_top.print_topology();
endfunction

What ordering IS guaranteed

  1. All build_phase complete before any connect_phase begins.

  2. All connect_phase complete before end_of_elaboration begins.

  3. All function build-time phases finish before run_phase starts.

  4. All run_phase activity completes (per objections) before extract begins.

What ordering is NOT guaranteed

  • Sibling order within build_phase on driver vs monitor.

  • Order of independent agents under the same env.

  • Order of unrelated analysis port subscribers.

Key takeaways

  • Print PHASE logs once — traversal direction becomes intuitive.

  • end_of_elaboration topology print is the structural sign-off point.

  • Never encode sibling-order assumptions into reusable VIP code.

Common pitfalls

  • Using associative array iteration order as build order.

  • env connect_phase wiring before child agent connect — actually OK (bottom-up hits children first).

  • Confusing bottom-up connect with 'connect children only' — parents still connect.