start_of_simulation Setup: Banners, Config, and Arming

Last function phase before run

start_of_simulation_phase is the human-facing setup moment : print what test is running, what config was resolved, and arm anything that must be ready when run_phase begins.

class base_test extends uvm_test;
  function void start_of_simulation_phase(uvm_phase phase);
    super.start_of_simulation_phase(phase);
    `uvm_info("BANNER",
      {"\n========================================\n",
       $sformatf("  TEST: %s\n", get_type_name()),
       $sformatf("  SEED: %0d\n", $get_initial_random_seed()),
       $sformatf("  TIME: %0t\n", $time),
       "========================================"},
      UVM_LOW)
    cfg.print();
    report_active_overrides();
  endfunction
endclass

[PHASE][UVM] start_of_simulation top-down flow

test.start_of_simulation   → global banner + cfg dump
  env.start_of_simulation    → env-specific settings log
    agent.start_of_simulation → per-agent mode banner (optional)

Key takeaways

• Banners and cfg dumps make logs self-documenting for triage.

• Top-down order means test announces before children.

• Arm watchdogs here — not drive stimulus.

Common pitfalls

• Starting sequences in start_of_simulation — belongs in run_phase.

• Dumping cfg at UVM_DEBUG only — invisible in default regressions.

• Omitting seed from banner — unreproducible failure reports.

Setup patterns beyond banners

Production testbenches use start_of_simulation for watchdog arming, plusarg summary, and checker mode selection.

Watchdog and checker arming

function void start_of_simulation_phase(uvm_phase phase);
  super.start_of_simulation_phase(phase);
  env.sb.set_compare_mode(cfg.sb_mode);
  env.arm_protocol_watchdog(cfg.watchdog_cycles);
  `uvm_info("PLUSARGS", plusarg_summary(), UVM_LOW)
endfunction

[PHASE] arming vs driving

ARM (OK in start_of_simulation):
  - set checker compare mode
  - load coverage exclusion file path
  - register callback hooks
  - snapshot cfg to report database

DRIVE (NOT OK):
  - assert reset
  - wait for clock edge
  - launch sequences

Config snapshot for regression DB

function void start_of_simulation_phase(uvm_phase phase);
  super.start_of_simulation_phase(phase);
  regression_db.record_run(
    .test_name(get_type_name()),
    .seed($get_initial_random_seed()),
    .cfg_snapshot(cfg.serialize())
  );
endfunction

• Serialize cfg once — same snapshot in log and regression DB.

• Log plusarg overrides that modified cfg after build.

• Include git hash or build ID in banner when available.

[PHASE][UVM] start_of_simulation content template

========================================
TEST:    smoke_sanity_test
SEED:    12345
BUILD:   abc1234
AGENTS:  tx=ACTIVE rx=PASSIVE
SB:      ON  COV: ON
========================================

Common pitfalls

• Randomizing cfg in start_of_simulation — structure already frozen.

• Arming watchdog that consumes time internally.

• Child banner before test banner — confusing log order if super skipped.