Part 2 · Phases & Lifecycle · Intermediate

Phase Mismatch Symptoms: Signatures, Super, Overrides

Silent failures from wrong phase method signatures, missing super calls, and factory overrides that never fire.

Wrong signature = silent no-op

UVM phase callbacks are virtual methods with exact signatures. A typo — wrong argument type, missing uvm_phase phase parameter, or misspelled phase name — creates a new method that never gets called by the scheduler. No compile error. No runtime warning.

systemverilog
// BUG: typo — this is NOT an override
function void build_phsae(uvm_phase phase);  // misspelled
  super.build_phase(phase);
endfunction

// BUG: wrong argument — NOT an override
function void build_phase(int phase);
  super.build_phase(phase);
endfunction
systemverilog
// CORRECT signature
function void build_phase(uvm_phase phase);
  super.build_phase(phase);
  // your code
endfunction
  • Use compiler override warnings (-warn=nooverride or equivalent) where available.

  • Add a unique uvm_info in each phase override to confirm it ran.

  • Compare against uvm_component base class signatures exactly.


Missing super

systemverilog
// BUG: child build never runs
function void build_phase(uvm_phase phase);
  // super.build_phase(phase);  MISSING
  my_child = child_c::type_id::create("child", this);
endfunction

Skipping super.build_phase means children in the sub-hierarchy are never created. Skipping super.connect_phase means child TLM wiring is skipped. The symptom is missing components or unconnected ports.

Override registration timing

systemverilog
// BUG: override after child already built
function void build_phase(uvm_phase phase);
  super.build_phase(phase);   // creates child with original type
  child_c::type_id::set_type_override(my_child_c::get_type());
endfunction
systemverilog
// FIX: override in test constructor or before super.build
function new(string name, uvm_component parent);
  super.new(name, parent);
  child_c::type_id::set_type_override(my_child_c::get_type());
endfunction

Key takeaways

  • Signature typo = silent no-op; add phase-entry log to every override.

  • Always call super unless you have a documented reason not to.

  • Register factory overrides before the target is created.

Common pitfalls

  • Copy-paste phase method with wrong phase name in function name.

  • Assuming override worked because compile passed.


Confirmation pattern

systemverilog
function void build_phase(uvm_phase phase);
  `uvm_info("PHASE_CHK", "my_comp.build_phase entered", UVM_HIGH)
  super.build_phase(phase);
endfunction

During development, leave PHASE_CHK logs at UVM_HIGH. A missing log line immediately identifies silent override failures.