Timed mock (45 minutes)

Reg block + adapter + frontdoor sequence.

Timer breakdown

1. 0–5 min: Reg spec — 3 registers fields

2. 5–15 min: Reg block + map sketch

3. 15–30 min: reg2bus/bus2reg adapter on APB

4. 30–40 min: Frontdoor write/read sequence

5. 40–45 min: Mirror check + peek mention

RUBRIC (score 1–5 each)

  Mechanism accuracy — correct UVM pattern, no magic
  Communication — narrates while sketching
  Pitfalls — cites unprompted
  Test mindset — smoke test + regression hook

STRONG HIRE: mechanism + pitfall + test without prompting
NO HIRE: silent coding, wrong TLM direction, no test plan

Interviewer follow-up traps (sample 10)

• Endianness?

• RO field write attempt?

• Backdoor when?

• Adapter vs predictor?

• Reset mirror values?

Strong hire signals

• Narrates DECLARE→TEST without prompting

• Names pitfall unprompted

• Smoke test and regression hook stated

• Asks clarifying protocol questions early

No hire signals

• Silent coding

• Wrong TLM direction on diagram

• No test plan after sketch

• Cannot recover when stuck

CODE LAB FOLLOW-UP: uvm-l10-mock-ral

Key takeaways

• Complete mock in 45 min wall clock.

• Self-score rubric honestly.