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Course contents

  • Start Here4
  • UVM Foundations14
  • UVM Phases & Simulation Lifecycle26
  • Factory & Configuration15
  • Transaction-Level Modeling (TLM)13
  • UVM Sequences & Stimulus21
  • UVM Agents & Protocol VIP21
  • Environment & Test Classes11
  • Checking & Coverage in UVM21
  • UVM Register Abstraction Layer (RAL)22
  • Advanced UVM in Practice13
  • Debug & Regression10
  • Coding Practice47
    • How to Use This Course
    • Whiteboard Delivery Framework
    • Scoreboard Coding
    • Monitor & Driver Coding
    • Sequences Coding
    • TLM & Analysis
    • RAL & Adapters
    • Factory & config_db
    • Phases & Objections
    • Env & Test Architecture
    • Debug Broken Testbench
    • Mock Interview Sets
    • Senior UVM Coding Cheat Sheet
  • Verification in Industry Practice10
  • Senior Prep: Architecture, Leadership and Interviews32
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←Coding Practice
  1. Topics
  2. UVM Verification
  3. Coding Practice
  4. Senior UVM Coding Cheat Sheet
On this page

    UVM Coding PracticeSenior

    Senior UVM Coding Cheat Sheet

    One-page patterns: macros, phases, config_db, TLM, sequences, scoreboard, RAL, factory, pitfalls.

    Class macros

    design.sv
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    `uvm_component_utils(my_comp)
    `uvm_object_utils(my_item)
    `uvm_declare_p_sequencer(my_sqr)
    `uvm_field_int(addr, UVM_ALL_ON)

    Phases + objections

    Diagram
    build → connect → end_of_elaboration → start_of_simulation
    → run (reset/configure/main/shutdown) → extract → check → report
    
    task run_phase(uvm_phase phase);
      phase.raise_objection(this);
      // stimulus
      phase.phase_done.set_drain_time(this, 100);
      phase.drop_objection(this);
    endtask

    config_db

    design.sv
    uvm_config_db#(apb_vif)::set(this, "env.agent*", "vif", vif);
    uvm_config_db#(apb_vif)::get(this, "", "vif", vif);
    uvm_config_db#()::dump();

    TLM

    design.sv
    uvm_analysis_port #(txn) ap;
    uvm_analysis_imp_act #(txn, sb) act_imp;
    mon.ap.connect(sb.act_imp);

    Sequence body

    design.sv
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    virtual task body();
      repeat (N) begin
        pkt req = pkt::type_id::create("req");
        start_item(req);
        assert(req.randomize());
        finish_item(req);
      end
    endtask

    Scoreboard analysis imp

    design.sv
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    function void write_act(txn t);
      act_q.push_back(t);
      if (exp_q.size()) compare(exp_q[0], act_q[0]);
    endfunction

    Reg adapter skeleton

    design.sv
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    virtual function void reg2bus(uvm_reg_item rw, ref bus_txn bus);
      bus.addr = rw.addr;
      bus.data = rw.data[0];
      bus.write = (rw.kind != UVM_READ);
    endfunction

    Factory override

    design.sv
    pkt::type_id::set_type_override(derived_pkt::get_type());
    // BEFORE create of pkt

    Top 10 interview pitfalls

    • config_db path typo → null vif

    • Missing item_done → seq hang

    • Objection leak → sim never ends

    • Factory override after create

    • Head-only scoreboard on OOO bus

    • reg2bus vs bus2reg reversed

    • Compare before reset flush

    • analysis port not connected

    • Silent whiteboard — no narration

    • No smoke test after sketch

    Key takeaways

    • Print or copy this page before mock interviews.

    • Pair with Code lab level 8–10 drills.

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    See also

    • How to Use This Course
    • Whiteboard Delivery Framework
    • Scoreboard Coding