Timed mock (60 minutes)

Monitor reconstruct + driver + basic sequence for AXI-lite sanity.

Timer breakdown

1. 0–10 min: Clarify AXI-lite channels (AR/R vs AW/W/B)

2. 10–25 min: Monitor txn reconstruct on paper

3. 25–40 min: Driver get_next_item + valid/ready

4. 40–50 min: Basic rand write/read sequence

5. 50–60 min: One SVA or checker mention + smoke

RUBRIC (score 1–5 each)

  Mechanism accuracy — correct UVM pattern, no magic
  Communication — narrates while sketching
  Pitfalls — cites unprompted
  Test mindset — smoke test + regression hook

STRONG HIRE: mechanism + pitfall + test without prompting
NO HIRE: silent coding, wrong TLM direction, no test plan

Interviewer follow-up traps (sample 10)

• Outstanding reads count?

• Response interleaving?

• WSTRB on narrow transfer?

• Reset behavior?

• Timeout policy?

Strong hire signals

• Narrates DECLARE→TEST without prompting

• Names pitfall unprompted

• Smoke test and regression hook stated

• Asks clarifying protocol questions early

No hire signals

• Silent coding

• Wrong TLM direction on diagram

• No test plan after sketch

• Cannot recover when stuck

CODE LAB FOLLOW-UP: uvm-l10-mock-axi-lite

Key takeaways

• Complete mock in 60 min wall clock.

• Self-score rubric honestly.