The parts are in learning order, and reading them in order is the best route if you have the time. If you do not, pick the path that fits the work you want to do. Every lesson below is a link, numbered as in its part.
No HDL, Linux or Git. All forty lessons in order, with the exercises and the code. If the first listings look unfamiliar, keep the Syntax Primer open beside Lesson 1.2:
[Part 1: How Chips Get Made](start-here/how-chips-get-made): 1.1 Idea to Silicon, 1.2 What RTL Is, 1.3 ASIC, FPGA, SoC and IP, 1.4 Front-End and Back-End: Who Does What, 1.5 PPA Primer, 1.6 What Happens After RTL
[Part 2: Your Workstation](start-here/workstation): 2.1 Shell Survival Kit, 2.2 Files, Paths and Layout, 2.3 Git: Save, Compare, Undo, 2.4 Installing and Checking Tools, 2.5 Reading Tool Messages
[Part 3: Specify and Architect](start-here/specify-and-architect): 3.1 Writing a Testable Spec, 3.2 From Spec to Microarchitecture, 3.3 Golden Model and Register Contract
[Part 4: The Design Loop](start-here/design-loop): 4.1 Compile, Elaborate, Simulate, Synthesize, Lint, 4.2 First Simulation, 4.3 Waveforms with GTKWave, 4.4 Lint with Verilator, 4.5 First Synthesis Check, 4.6 Simulation Code vs Synthesizable Code
[Part 5: The Verification Ladder](start-here/verification-ladder): 5.1 Tests That Can Fail, 5.2 Self-Checking and Golden Model, 5.3 Random Stimulus and Seeds, 5.4 Assertions, 5.5 Coverage, 5.6 Formal in One Lesson
[Part 6: Automation and Reproducibility](start-here/automation): 6.1 Makefile for the Loop, 6.2 Exit Codes and Pass Markers, 6.3 CI Smoke Test, 6.4 Pinning Tool Versions, 6.5 Smoke vs Nightly
[Part 7: Hand-Off to the Back-End](start-here/handoff): 7.1 What the Back-End Needs, 7.2 Reading a Constraints File, 7.3 The Release Package
[Part 8: When Things Go Wrong](start-here/when-things-go-wrong): 8.1 Troubleshooting Table, 8.2 Debug Habits, 8.3 Beginner Mistakes Checklist
[Part 9: Project and Next Steps](start-here/project-and-next): 9.1 Project: Spec to Green CI, 9.2 Project Review and Rubric, 9.3 Where to Go Next
Skim Part 1, set up quickly in Part 2, then focus on spec, the design loop, automation and hand-off:
1.5 PPA Primer, 1.6 What Happens After RTL (skim the rest of Part 1)
2.4 Installing and Checking Tools, 2.5 Reading Tool Messages
3.1 Writing a Testable Spec, 3.2 From Spec to Microarchitecture, 3.3 Golden Model and Register Contract
4.1 Compile, Elaborate, Simulate, Synthesize, Lint, 4.2 First Simulation, 4.3 Waveforms with GTKWave, 4.4 Lint with Verilator, 4.5 First Synthesis Check, 4.6 Simulation Code vs Synthesizable Code
6.1 Makefile for the Loop, 6.2 Exit Codes and Pass Markers, 6.3 CI Smoke Test, 6.4 Pinning Tool Versions
7.1 What the Back-End Needs, 7.2 Reading a Constraints File, 7.3 The Release Package
9.1 Project: Spec to Green CI, 9.2 Project Review and Rubric
Spec and the loop first, then the full ladder, with automation and debug habits holding it together:
3.1 Writing a Testable Spec, 3.3 Golden Model and Register Contract
4.2 First Simulation, 4.3 Waveforms with GTKWave, 4.6 Simulation Code vs Synthesizable Code
5.1 Tests That Can Fail, 5.2 Self-Checking and Golden Model, 5.3 Random Stimulus and Seeds, 5.4 Assertions, 5.5 Coverage, 5.6 Formal in One Lesson
6.1 Makefile for the Loop, 6.2 Exit Codes and Pass Markers, 6.3 CI Smoke Test