You can run the loop. What should you learn next?
You carried pulse_counter from a written spec to a green build and graded it against the rubric. That loop, spec to model to testbench to RTL to automation, is the whole front end in miniature. The deep courses each take one station of that loop and teach it at full size. The map below matches the station you want to the course that owns it.
The figure below puts this course in the middle and the next courses around it, grouped by the work you want to do. Find the sentence that sounds like your job, then follow its links. Every link below goes to a course that owns its subject; this course stops where those begin.
The menu below is long on purpose, but you only need one course now. Find the row that matches the work you expect to do, take that course, and check the readiness criterion first: it names what you should be able to do from this course before the next one will feel fair.
If you want to | Take next | Ready when you can |
|---|---|---|
Design hardware | write a spec with checkable criteria and get | |
Verify designs | explain what a surviving mutant means and add a directed check that kills one | |
Learn the full language | read the course testbench and assertions without looking up the syntax | |
Understand what RTL becomes | read a synthesis log and a constraints file line by line | |
Find bugs faster | go from a failing seed to the edge that exposes the bug using a waveform |
If none of these rows fits, the longer map below groups every course by goal.
Each group below names a goal, the courses that serve it, and one reason per course. Start with the goal that matches the work you want next.
Write better RTL. The RTL Design course teaches synthesizable logic at full size, past one counter. The SystemVerilog course teaches the full language behind your testbench and your assertions.
Verify like a professional. The Verification First Principles course teaches checking strategy from spec to sign-off. The UVM course teaches the reusable testbench method that teams use. The Formal course teaches proofs that reach the cases simulation cannot.
Meet timing. The STA course teaches reading timing reports and closing timing. The Synthesis course teaches what your RTL becomes in gates. The PD course teaches what happens after your release package.
Cross clock domains safely. The CDC/RDC course teaches moving signals between clocks without losing them, the first subject this course names and never teaches.
Test and power. The DFT course teaches designing so the chip stays testable after fabrication. The Low-Power course teaches power intent from spec to implementation.
Debug real failures. The Hardware Debug course teaches the loop that finds a bug when the waveform is all you have.
Build bigger systems. The CPU Design course and the RISC-V Design course teach processors as the next design. The SoC course teaches many blocks on one chip. The Protocol course teaches interfaces as evidence, never as the subject.
Every deep course rewards the same habits this project built. A timing constraint is a spec written for tools instead of people, and it deserves the same reading care. A coverage goal is an acceptance criterion with a number attached. A failing nightly regression asks the same question your mutants asked: does this test still fail when it should.
Bring the artifacts too, not only the habits. Your Makefile pattern ports to any block, your versions page ports to any project, and your rubric ports to any review. The tools change with the station; the loop stays the same shape.
Pick by the role you want, not by curiosity. The reading paths page already sorts this course three ways: complete beginner, RTL designer, and verification engineer. Extend that choice outward: designers go to RTL and SystemVerilog first, verifiers to Verification First Principles and UVM, and anyone facing a slow chip to STA.
Take one course at a time, and finish the loop in each one. A second course started before the first one pays off splits the habit this course built: one spec, one build, one verdict. Depth in one station beats tours of five.
Collecting course hubs instead of finishing one. Reading seven introductions feels like progress and proves nothing. Enroll in one course, run its loop, and let the rubric habit grade you there.
Retreating to comfort when the next course gets hard. Rereading this course is review, not progress. When the new material resists, shrink the case and reproduce first, exactly as the debug habits taught.
Borrowing a back-end tool as a front-end shortcut. Synthesis and physical design answer the questions this course hands off; they do not replace the loop. Green simulation with red timing is still red.
Rule: finish one loop before you start the next.
The RTL Design course, because it teaches synthesizable logic at full size, which is the work itself. SystemVerilog follows for language depth. Verification courses can wait until the design habit is solid.
The CDC/RDC course, because safe clock crossing is its subject and this course never teaches it. You bring the spec-first habit and a testbench that checks behavior on both sides of the crossing.
This course taught the whole front-end loop in miniature; each deep course teaches one station at full size.
Pick the next course by the role you want, and start with the goal that matches your work.
Finish one loop before you start the next; depth in one station beats tours of five.