SystemVerilog OOP Mastery · All levels
Abstract & Interface Classes
How SystemVerilog uses `virtual class` and `interface class` to define contracts, enforce implementation intent, and emulate multiple-inheritance style reuse without C++-style class diamond hazards.
What this section covers
How SystemVerilog uses `virtual class` and `interface class` to define contracts, enforce implementation intent, and emulate multiple-inheritance style reuse without C++-style class diamond hazards.
Topics
diagram
- Abstract Classes with `virtual class`
- Pure Virtual Methods as Compile-Time Contracts
- Interface Classes and `implements`
- No Multiple Inheritance: Interface Classes + Composition