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Part 0 · Start Here · Beginner

This part takes about 40 minutes. It does not teach SystemVerilog yet. It sets you up so the rest of the course reads easily.

Lesson	You will
Who This Course Is For	Check you have the Verilog you need, and pick a path.
How the Lessons and Examples Work	Run an example, read its verdict, and break it on purpose.
Words You Will Meet	Get a one-line meaning for each testbench word, and where it is taught.
The Testbench Picture	See the four jobs every self-checking testbench does.
The PacketFIFO Project	Meet the design you will verify, piece by piece, through the course.
What the Open Simulators Run	Reference: which features the free tools run correctly. Come back to it from Parts 3 to 5.

Check yourself Do you need to know UVM before this course?

No. This course teaches the SystemVerilog that UVM is built from. The UVM course comes after it.

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