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Course contents

  • Start Here6
    • Who This Course Is For
    • How the Lessons and Examples Work
    • Words You Will Meet
    • The Testbench Picture
    • The PacketFIFO Project
    • What the Open Simulators Run
  • SystemVerilog Language Foundations28
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive36
  • SystemVerilog Assertions — Interview-Critical Deep Dive40
  • Functional Coverage in SystemVerilog22
  • Testbench Architecture in SystemVerilog23
  • Advanced Language & Integration25
  • Senior & Interview Preparation21
  • Principal-Level Verification28
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‹Start Here
  1. Topics
  2. SystemVerilog
  3. Start Here
  4. Words You Will Meet

Part 0 · Start Here · Beginner

Words You Will Meet

One-line meanings for the verification words the course uses, and the lesson that teaches each one properly.

On this page

    Why this matters

    Verification words such as driver, monitor and scoreboard appear long before the lessons that teach them. A one-line meaning stops a new word from blocking the idea it is used to explain.

    After this lesson you can: give a one-line meaning for each common testbench and SystemVerilog word, and find the lesson that teaches it.

    Verification has its own vocabulary, and some words appear before the lesson that teaches them. When that happens, the meaning below is enough to keep reading.

    The testbench words

    Word

    One-line meaning

    Taught in

    DUT

    The design under test: the RTL being checked.

    The Testbench Picture

    Testbench

    Code that drives the DUT, checks its outputs and reports a verdict. It is not built into hardware.

    The Testbench Picture

    Stimulus

    The input values and sequences the testbench applies.

    Stimulus (Part 7)

    Reference model

    Code that computes the right answer from the spec, to compare against the DUT.

    Reference Models (Part 7)

    Transaction

    One operation described as data, such as one packet or one bus write, instead of as pin wiggles.

    Class Declaration & Objects (Part 2)

    Driver

    The part that turns transactions into pin activity on the DUT inputs.

    Driver Design (Part 7)

    Monitor

    The part that watches pins and rebuilds transactions from what happened. It never drives.

    Monitor Design (Part 7)

    Scoreboard

    The part that compares what the monitor saw with what the reference model expected.

    Scoreboard Architecture (Part 7)

    The SystemVerilog words

    Word

    One-line meaning

    Taught in

    Interface

    A named bundle of signals that connects a testbench to a DUT in one port.

    Interfaces (Part 1)

    Class, object, handle

    A class is a type; new builds an object from it at run time; a handle is a variable that points at an object.

    Classes, Objects & Handles (Part 2)

    Virtual interface

    A handle to an interface, so class code can reach DUT pins.

    Virtual Interfaces (Part 2)

    rand, constraint, randomize()

    Fields the solver fills with random values that obey rules you write.

    Randomization (Part 3)

    Seed

    The starting number of the random generator. The same seed repeats the same run.

    Random Stability and Seeding (Part 3)

    Assertion

    A rule about signal behaviour over clock cycles that the simulator checks all the time.

    Assertions (Part 4)

    Coverage

    A record of which planned scenarios actually happened during the runs.

    Functional Coverage (Part 5)

    Regression

    Many tests and seeds run together, with one pass or fail summary.

    The Regression Flow (Part 7)

    UVM

    A standard library of testbench classes built from these same ideas. It has its own course.

    UVM course

    Check yourself What is the difference between a monitor and a driver?

    A driver puts values on the DUT inputs. A monitor only watches pins and reports what happened. If a monitor drove anything, the testbench would be checking its own stimulus instead of the DUT.

    Check yourself Why does a scoreboard need a reference model?

    To know what the right answer is. The scoreboard compares two streams: what the DUT did (from the monitor) and what it should have done (from the reference model).

    Remember

    • A driver drives the DUT inputs; a monitor only watches; a scoreboard compares.

    • A transaction is one operation described as data, not as pin wiggles.

    • Class, object, handle: the type, the thing new builds, and the variable that points at it.

    Rule of thumb: when a lesson uses a word you have not met, look it up here, then keep reading.

    How this was checked

    Every Taught in link was checked against the course page list on 2026-10-18.

    Related topics

    • Next: The Testbench Picture

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    See also

    • Who This Course Is For
    • The PacketFIFO Project
    • What the Open Simulators Run