The course assumes you can read basic Verilog. You do not need to know any SystemVerilog, classes or verification yet.
You should be able to read | Example |
|---|---|
A module with inputs and outputs |
|
Continuous assignment |
|
A clocked always block with reset |
|
if, case and nonblocking assignment |
|
Vectors and widths |
|
If any row is new, take RTL Foundations first. It teaches exactly these, and it uses the same kind of runnable examples.
Read the counter and its testbench below. The testbench drives the inputs, waits for clock edges, and checks the output twice.
module count4 (
input wire clk,
input wire rst,
input wire en,
output reg [3:0] q
);
always @(posedge clk)
if (rst) q <= 4'd0;
else if (en) q <= q + 4'd1;
endmodule
module tb_count4;
reg clk = 0, rst = 1, en = 0;
wire [3:0] q;
integer errors = 0;
count4 dut (.clk(clk), .rst(rst), .en(en), .q(q));
always #5 clk = ~clk;
initial begin
@(negedge clk) rst = 0;
@(negedge clk) en = 1;
repeat (3) @(negedge clk);
if (q !== 4'd3) errors = errors + 1; // first check
en = 0;
repeat (2) @(negedge clk);
if (q !== 4'd3) errors = errors + 1; // second check
if (errors == 0) $display("PASS: count4 counted 3 enabled edges and held while disabled");
else $fatal(1, "FAIL: count4 ended at %0d", q);
$finish;
end
endmodulePASS: count4 counted 3 enabled edges and held while disabled3 at both checks. After en goes to 1, three rising edges arrive before the first check, and each adds 1. Then en is 0, so the next two edges leave q alone.
This is the output the simulator printed:
PASS: count4 counted 3 enabled edges and held while disabledIf you could follow the timing and got 3 before revealing the answer, you are ready. If negedge, repeat or !== was unclear, the first lessons of Part 1 cover the SystemVerilog parts, and RTL Foundations covers the Verilog parts.
You are | Start with | Then |
|---|---|---|
New to verification | This part, then Parts 1 to 3 in order | Parts 4 to 7 in order; Part 8 when you prepare for interviews |
Already writing directed testbenches | Part 2 (OOP) and Part 3 (Randomization) | Part 7 (Testbench) to build a class testbench, then Parts 4 and 5 |
Preparing for a senior interview | Part 8 (Senior) | Part 9 (Principal); dip back into a part when a question exposes a gap |
q !== 4'd3 and not q != 4'd3?!== also treats an unknown X as different. If q were never reset it would read X, and != would give X, which an if treats as false: the check would silently pass. Part 1 explains X and these operators.
Run with Icarus Verilog 13 (iverilog -g2012) and Verilator 5.048 (--binary --timing) on 2026-10-18; both printed the PASS line shown, with no warnings.
The readiness check proves the counter for this one input sequence only; it is a reading exercise, not a full verification.