SystemVerilog OOP Mastery · All levels
Abstract Classes with `virtual class`
A `virtual class` is an abstract base: it can carry shared state/behavior, but it cannot be constructed directly.
Overview
A `virtual class` is an abstract base: it can carry shared state/behavior, but it cannot be constructed directly.
Use `virtual class` when you want a strong architectural boundary: all real objects must be specific derived types, but common data, utility methods, and protocol hooks stay centralized in one base definition.
In this topic
diagram
1. Concept Explained
2. Code Examples
3. SystemVerilog vs C++/Java
4. Pitfalls
5. Exercises
6. Interview QuestionsRead the concept first, study the code examples, compare against C++/Java, then test yourself with the exercises and interview questions.
Virtual dispatch table resolution
diagram
VIRTUAL DISPATCH TABLE (VTABLE STYLE)
handle type: component object type: axi_driver
+----------------------+ +------------------------+
| component handle c |--->| vptr ----------------+----+
+----------------------+ +------------------------+ |
v
+----------------------------+
| axi_driver vtable |
| [0] build_phase() |
| [1] run_phase() override |
| [2] report_phase() |
+----------------------------+
c.run_phase() resolves through vptr at runtime, not handle static type.