SystemVerilog OOP Mastery · All levels
No Multiple Inheritance: Interface Classes + Composition
SystemVerilog has single class inheritance; emulate mixin-style behavior using interface-class contracts plus composed helper objects.
Overview
SystemVerilog has single class inheritance; emulate mixin-style behavior using interface-class contracts plus composed helper objects.
SV intentionally avoids C++-style multiple class inheritance, so you never resolve ambiguous base methods or duplicate base sub-objects. The trade-off is that shared capabilities must be modeled explicitly.
In this topic
diagram
1. Concept Explained
2. Code Examples
3. SystemVerilog vs C++/Java
4. Pitfalls
5. Exercises
6. Interview QuestionsRead the concept first, study the code examples, compare against C++/Java, then test yourself with the exercises and interview questions.
Virtual dispatch table resolution
diagram
VIRTUAL DISPATCH TABLE (VTABLE STYLE)
handle type: component object type: axi_driver
+----------------------+ +------------------------+
| component handle c |--->| vptr ----------------+----+
+----------------------+ +------------------------+ |
v
+----------------------------+
| axi_driver vtable |
| [0] build_phase() |
| [1] run_phase() override |
| [2] report_phase() |
+----------------------------+
c.run_phase() resolves through vptr at runtime, not handle static type.