SystemVerilog OOP Mastery · All levels
Randomization with Constraints
SystemVerilog randomization combines rand and randc members with constraint blocks and inline with-clauses for scenario control.
Overview
SystemVerilog randomization combines rand and randc members with constraint blocks and inline with-clauses for scenario control.
rand variables are solved each randomize call subject to active constraints. randc variables cycle through all values in their domain before repeating, which is useful for small enumerated spaces.
In this topic
diagram
1. Concept Explained
2. Code Examples
3. SystemVerilog vs C++/Java
4. Pitfalls
5. Exercises
6. Interview QuestionsRead the concept first, study the code examples, compare against C++/Java, then test yourself with the exercises and interview questions.
Deep copy versus shallow copy
diagram
DEEP VS SHALLOW COPY
source txn s
|
+-- payload_handle -----> payload object @0x3000
shallow copy: txn t = s;
t.payload_handle --------^ (same nested object)
deep copy: t.copy(s);
t.payload_handle -----> payload object @0x4100 (new clone)
Shallow copy duplicates handles. Deep copy duplicates reachable object graph.