SystemVerilog OOP Mastery · All levels
Shallow vs Deep Copy
SystemVerilog class assignment is handle assignment, so true object duplication requires explicit deep-copy logic for nested handles.
Overview
SystemVerilog class assignment is handle assignment, so true object duplication requires explicit deep-copy logic for nested handles.
A class variable in SystemVerilog stores a handle, not an in-place object value. Because of that, dst = src copies only the handle, and both names refer to the same underlying object.
In this topic
diagram
1. Concept Explained
2. Code Examples
3. SystemVerilog vs C++/Java
4. Pitfalls
5. Exercises
6. Interview QuestionsRead the concept first, study the code examples, compare against C++/Java, then test yourself with the exercises and interview questions.
Deep copy versus shallow copy
diagram
DEEP VS SHALLOW COPY
source txn s
|
+-- payload_handle -----> payload object @0x3000
shallow copy: txn t = s;
t.payload_handle --------^ (same nested object)
deep copy: t.copy(s);
t.payload_handle -----> payload object @0x4100 (new clone)
Shallow copy duplicates handles. Deep copy duplicates reachable object graph.