Shallow vs Deep Copy: Concept Explained

Concept

In short: SystemVerilog class assignment is handle assignment, so true object duplication requires explicit deep-copy logic for nested handles.

A class variable in SystemVerilog stores a handle, not an in-place object value. Because of that, dst = src copies only the handle, and both names refer to the same underlying object.

Using new src allocates a new top-level object and performs member-wise copy, but member-wise copy of class-typed members still copies handles. This is why nested objects remain shared unless your copy flow recursively allocates and copies them.

Verification bugs show up when monitors, scoreboards, and predictors store what they think is a snapshot but actually store aliases. A later mutation from another component silently changes history.

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