SystemVerilog OOP Mastery · All levels

Inheritance & Polymorphism: Tricky Q&A

Rapid-fire interview Q&A for Inheritance & Polymorphism.

Section Q&A

Rapid-fire interview questions for Inheritance & Polymorphism. Answer out loud, then check yourself.

Q1. A derived class defines report(), but base_handle.report() still calls the base method. What is the root cause?

Answer: report is not declared virtual in the base class, so dispatch is static for calls through a base handle. Child same-name methods do not change that without a virtual base declaration.

Trap: Believing same-name methods always dispatch dynamically.

Q2. Why does UVM extension architecture emphasize virtual phase and do_* methods?

Answer: Factory and framework flows usually operate through base handles. Virtual hooks are the mechanism that lets derived classes alter runtime behavior while keeping infrastructure generic.

Trap: Thinking factory override alone guarantees behavioral override.

Q3. What does super.new protect against in inheritance-heavy testbench code?

Answer: It preserves parent initialization contracts so inherited fields, object handles, and metadata are valid before child logic executes.

Trap: Treating super.new as optional boilerplate.

Q4. How do you combine reusable capabilities when SV disallows multiple class inheritance?

Answer: Use one purposeful extends chain, add interface-class contracts for role APIs, and compose helper objects for orthogonal behavior.

Trap: Forcing unrelated behaviors into a deep single inheritance ladder.