SystemVerilog OOP Mastery · All levels
Class Inheritance with `extends`
SystemVerilog supports only single class inheritance, so reusable design depends on a clean base-class contract plus composition for orthogonal behavior.
Overview
SystemVerilog supports only single class inheritance, so reusable design depends on a clean base-class contract plus composition for orthogonal behavior.
A class in SystemVerilog can extend exactly one parent class. This avoids ambiguous method resolution and diamond-style state duplication, but it also means engineers must plan the inheritance tree intentionally. Keep the base class focused on shared invariants and expose extension points through protected state plus virtual methods where runtime customization is needed.
In this topic
1. Concept Explained
2. Code Examples
3. SystemVerilog vs C++/Java
4. Pitfalls
5. Exercises
6. Interview QuestionsRead the concept first, study the code examples, compare against C++/Java, then test yourself with the exercises and interview questions.
Inheritance hierarchy and substitution
INHERITANCE TREE
+-------------------+
| class component |
+---------+---------+
|
+------------+-------------+
| |
+---------v---------+ +---------v---------+
| class driver | | class monitor |
+---------+---------+ +-------------------+
|
+---------v---------+
| class axi_driver |
+-------------------+
Up-cast is legal: component c = new axi_driver();
Dynamic dispatch picks the most-derived virtual method.