SystemVerilog OOP Mastery · All levels
Class Inheritance with `extends`: Concept Explained
Concept Explained for Class Inheritance with `extends`.
Concept
In short: SystemVerilog supports only single class inheritance, so reusable design depends on a clean base-class contract plus composition for orthogonal behavior.
A class in SystemVerilog can extend exactly one parent class. This avoids ambiguous method resolution and diamond-style state duplication, but it also means engineers must plan the inheritance tree intentionally. Keep the base class focused on shared invariants and expose extension points through protected state plus virtual methods where runtime customization is needed.
Constructor chaining is central to correct inheritance. A derived constructor should call super.new first so inherited state is initialized before child-specific fields are touched. If the base class owns configuration defaults, random variables, or object handles, skipping or delaying super.new often creates null dereferences and inconsistent object identity in later phases.
When two features do not share a strict is-a relationship, prefer composition over deeper inheritance. In UVM this is common: a sequence item can inherit protocol fields from a base transaction while composing helper policy objects for CRC, addressing mode, or packing strategy. This keeps inheritance shallow and easier to debug.