SystemVerilog OOP Mastery · All levels
Polymorphism and Dispatch Semantics
Polymorphism in SV means a base handle can point to many derived object types, with behavior decided by virtual dispatch and safe downcast patterns.
Overview
Polymorphism in SV means a base handle can point to many derived object types, with behavior decided by virtual dispatch and safe downcast patterns.
A base-class handle referencing derived objects enables generic containers, APIs, and UVM framework flows. This is powerful for writing protocol-agnostic infrastructure: one queue of base handles can schedule many specialized implementations.
In this topic
diagram
1. Concept Explained
2. Code Examples
3. SystemVerilog vs C++/Java
4. Pitfalls
5. Exercises
6. Interview QuestionsRead the concept first, study the code examples, compare against C++/Java, then test yourself with the exercises and interview questions.
Inheritance hierarchy and substitution
diagram
INHERITANCE TREE
+-------------------+
| class component |
+---------+---------+
|
+------------+-------------+
| |
+---------v---------+ +---------v---------+
| class driver | | class monitor |
+---------+---------+ +-------------------+
|
+---------v---------+
| class axi_driver |
+-------------------+
Up-cast is legal: component c = new axi_driver();
Dynamic dispatch picks the most-derived virtual method.