SystemVerilog OOP Mastery · All levels
`super`, `super.new`, and Overriding Rules: Exercises
Exercises for `super`, `super.new`, and Overriding Rules.
Practice exercises
Exercise 1
A child UVM env overrides build_phase and creates monitors, but parent configuration fetch no longer happens. Fix the override.
Solution
diagram
Add super.build_phase(phase) at the top of the child build_phase, then keep monitor creation after the super call so parent config and child construction both execute.Exercise 2
Define class apb_cfg extends base_cfg where base_cfg initializes mode and timeout. Ensure apb_cfg adds wait_states safely.
Solution
diagram
In apb_cfg::new, call super.new(...) first so mode/timeout are valid, then initialize wait_states. Do not duplicate base initialization in child code.