SystemVerilog OOP Mastery · All levels
Virtual Methods and Override Intent
Only methods declared virtual in the base class participate in dynamic dispatch through base handles; non-virtual methods stay handle-type bound.
Overview
Only methods declared virtual in the base class participate in dynamic dispatch through base handles; non-virtual methods stay handle-type bound.
In SystemVerilog, virtual is opt-in polymorphism. If a base method is non-virtual, calls through a base handle resolve to the base implementation even when the object is actually derived. This is one of the most common confusion points for engineers coming from languages where overriding is virtual by default.
In this topic
1. Concept Explained
2. Code Examples
3. SystemVerilog vs C++/Java
4. Pitfalls
5. Exercises
6. Interview QuestionsRead the concept first, study the code examples, compare against C++/Java, then test yourself with the exercises and interview questions.
Inheritance hierarchy and substitution
INHERITANCE TREE
+-------------------+
| class component |
+---------+---------+
|
+------------+-------------+
| |
+---------v---------+ +---------v---------+
| class driver | | class monitor |
+---------+---------+ +-------------------+
|
+---------v---------+
| class axi_driver |
+-------------------+
Up-cast is legal: component c = new axi_driver();
Dynamic dispatch picks the most-derived virtual method.