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SystemVerilog OOP Mastery · All levels

Virtual Methods and Override Intent: Code Examples

Code Examples for Virtual Methods and Override Intent.

Code examples

Virtual vs non-virtual call behavior through base handle

systemverilog
class agent_base;
  function void report();
    $display("agent_base::report");
  endfunction

  virtual function void build_phase();
    $display("agent_base::build_phase");
  endfunction
endclass

class spi_agent extends agent_base;
  function void report();
    $display("spi_agent::report");
  endfunction

  virtual function void build_phase();
    $display("spi_agent::build_phase");
  endfunction
endclass

module tb;
  initial begin
    agent_base a;
    a = new spi_agent();
    a.report();      // non-virtual: calls agent_base::report
    a.build_phase(); // virtual: calls spi_agent::build_phase
  end
endmodule

Same-name methods do not imply dynamic dispatch. The base declaration must be virtual for runtime override selection.

UVM extension point relying on virtual override

systemverilog
class pkt_base extends uvm_sequence_item;
  `uvm_object_utils(pkt_base)

  function new(string name = "pkt_base");
    super.new(name);
  endfunction

  virtual function void do_print(uvm_printer printer);
    super.do_print(printer);
    printer.print_string("kind", "base");
  endfunction
endclass

class axi_pkt extends pkt_base;
  `uvm_object_utils(axi_pkt)
  rand bit [3:0] burst_len;

  function new(string name = "axi_pkt");
    super.new(name);
  endfunction

  virtual function void do_print(uvm_printer printer);
    super.do_print(printer);
    printer.print_field_int("burst_len", burst_len, 4, UVM_DEC);
  endfunction
endclass

UVM infrastructure usually manipulates objects through base handles. Declaring and overriding do_print as virtual ensures derived packet details appear during runtime debug.

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