SystemVerilog OOP Mastery · All levels

Virtual Methods and Override Intent: Concept Explained

Concept Explained for Virtual Methods and Override Intent.

Concept

In short: Only methods declared virtual in the base class participate in dynamic dispatch through base handles; non-virtual methods stay handle-type bound.

In SystemVerilog, virtual is opt-in polymorphism. If a base method is non-virtual, calls through a base handle resolve to the base implementation even when the object is actually derived. This is one of the most common confusion points for engineers coming from languages where overriding is virtual by default.

Overriding should preserve signature compatibility: method name, arguments, and return type must match override rules. For maintainability, many teams repeat the virtual keyword in derived methods to make intent explicit, even though the base declaration already controls dispatch.

Virtual methods are foundational in UVM because most framework extension points are base-handle calls (phase methods and do_* hooks). Factory overrides only become behaviorally useful when those hooks are virtual; otherwise the base implementation wins at runtime and your override appears ignored.

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