SystemVerilog OOP Mastery · All levels
Scenario: Missing Virtual Bug
A UVM environment passes unit smoke but fails in full regressions after a factory override rollout. Calls through base handles keep executing base methods, while direct child-handle tests still appear healthy.
Scenario
A UVM environment passes unit smoke but fails in full regressions after a factory override rollout. Calls through base handles keep executing base methods, while direct child-handle tests still appear healthy.
What to focus on
Mismatch between expected override execution count and observed base-method dispatch in regression traces.
Common traps
Assuming same-name methods dispatch dynamically without a virtual declaration on the base type.
Debugging factory registration first while the real issue is non-virtual base API.
Patching with adhoc casts instead of fixing the polymorphic contract.