SystemVerilog OOP Mastery · All levels
Callbacks and Policy Classes for Open Extension
Callbacks let you inject behavior at lifecycle hooks, while policy classes encapsulate algorithm choices; together they reduce inheritance forks and keep extension points explicit.
Overview
Callbacks let you inject behavior at lifecycle hooks, while policy classes encapsulate algorithm choices; together they reduce inheritance forks and keep extension points explicit.
Callbacks are event interception points. In UVM, they are powerful for pre/post behavior around a fixed owner component (driver, monitor, sequence) without cloning that component.\n\nPolicy classes are Strategy objects passed into a component so behavior is selected by composition. They are better when you need deterministic, inspectable algorithm switching (for example comparison rules or retry strategy).\n\nA practical rule: callbacks for cross-cutting hooks around existing control flow, policies for core decision logic that you want unit-testable and replaceable at integration time.
In this topic
1. Concept Explained
2. Code Examples
3. SystemVerilog vs C++/Java
4. Pitfalls
5. Exercises
6. Interview QuestionsRead the concept first, study the code examples, compare against C++/Java, then test yourself with the exercises and interview questions.
Factory override flow in verification
FACTORY OVERRIDE FLOW
test config
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+--> factory.set_type_override(base_driver, error_inject_driver)
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v
create("drv", parent, base_driver)
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v
+-------------------------------+
| instantiated: error_inject... |
+-------------------------------+
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v
virtual methods dispatch
Factory decouples call site from concrete class selection.