Parameterized Components and Agents at Scale

Overview

Parameterized UVM components preserve static type safety across multiple protocol families, enabling one architecture to scale without copy-paste VIP forks.

Parameterized classes turn transaction type into a compile-time contract. A single driver/agent architecture can support many item types while keeping sequencer-driver connections strongly typed.\n\nIn practice, teams use a generic shell plus protocol-specific typedef aliases. That gives clear integration names and avoids leaking long template specializations across the testbench.\n\nFactory behavior is specialization-specific: each `#(T)` specialization is its own type. Correct override strategy must target the exact specialization instantiated in hierarchy.

In this topic

1. Concept Explained
2. Code Examples
3. SystemVerilog vs C++/Java
4. Pitfalls
5. Exercises
6. Interview Questions

Read the concept first, study the code examples, compare against C++/Java, then test yourself with the exercises and interview questions.

Factory override flow in verification

FACTORY OVERRIDE FLOW

test config
   |
   +--> factory.set_type_override(base_driver, error_inject_driver)
                                   |
                                   v
                         create("drv", parent, base_driver)
                                   |
                                   v
                      +-------------------------------+
                      | instantiated: error_inject... |
                      +-------------------------------+
                                   |
                                   v
                          virtual methods dispatch

Factory decouples call site from concrete class selection.

Related topics

• OOP Patterns & UVM Application section

• SystemVerilog OOP Mastery hub